AMD Turion 64 Manuale operativo

Advanced Micro Devices

AMD Turion™ 64 Mobile Technology

Product Data Sheet

• Compatible with Existing 32-Bit Code Base

– Including supportforSSE,SSE2,SSE3*, MMX™,

3DNow!™technology,and legacy x86 instructions

*SSE3 supported by Rev. E and later processors

– Runs existing operating systems and drivers

– Local APIC on the chip

• AMD64 Technology

– AMD64 technology instruction set extensions

– 64-bit integer registers, 48-bit virtual addresses,

40-bit physical addresses

– Eight additional 64-bit integer registers (16 total)

– Eight additional 128-bit SSE registers (16 total)

• Enhanced Virus Protection

– No Execute (NX) bit in page-translation tables

specifies whether code can be executed from the

page

• HyperTransport™ Technology to I/O Devices

– One 16-bit link supporting speeds up to 800 MHz

(1600 MT/s) or 3.2 Gbytes/s in each direction

• 64-Kbyte 2-Way Associative ECC-Protected

L1 Data Cache

– Two 64-bit operations per cycle, 3-cycle latency

• 64-Kbyte 2-Way Associative Parity-Protected

L1 Instruction Cache

– With advanced branch prediction

• 16-Way Associative ECC-Protected

L2 Cache

– Exclusive cache architecture—storage in addition

to L1 caches

– Up to 1 Mbyte per L2 cache

– 1 Mbyte and 512-Kbyte options

• Machine Check Architecture

– Includes hardware scrubbing of major

ECC-protected arrays

754-Pin Package Specific Features

• Refer to the AMD Functional Data Sheet,

754-Pin Package, order# 31410, for functional,

mechanical, and electrical details of 754-pin

packages.

• Packaging

– 754-pin lidless micro PGA

– 1.27-mm pin pitch

– 29 x 29-row pin array

– 40 mm x 40 mm organic substrate

– Organic C4 die attach

• Integrated Memory Controller

– Low-latency, high-bandwidth

– 72-bitDDRSDRAMat100,133,166,and200MHz

– Supports up to two unbuffered SO-DIMMs

– ECC checking with double-bit detect and single-bit

correct

• Electrical Interfaces

– HyperTransport™ technology: LVDS-like

differential, unidirectional

– DDR SDRAM: SSTL_2 per JEDEC specification

– Clock, reset, and test signals also use DDR

SDRAM-like electrical specifications.

• Power Management

– Multiple low-power states including Deeper Sleep

(C3 with AltVID)

– System Management Mode (SMM)

– ACPI compliant, including support for processor

performance states

– AMD PowerNow!™ technology is designed to

dynamically switch between multiple low-power

states based on application performance

requirements.

32816Publication # 3.05Revision:

September 2006Issue Date:

32816 Rev. 3.05 September 2006

AMD Turion™ 64 Mobile Technology Product Data Sheet

Socket S1g1 Processor Specific

Features

• Refer to the Socket S1g1 Processor Functional

Data Sheet, order# 31731, for functional and

mechanical details of socket S1g1 processors.

Refer to the AMD NPT Family 0Fh Processor

Electrical Data Sheet, order# 31119, for

electrical details of socket S1g1 processors.

• Packaging

– 638-pin lidless micro PGA package

– 1.27-mm pin pitch

– 26 x 26 pin grid array

– 35 mm x 35 mm organic substrate

– Compliant with RoHS (EU Directive 2002/95/EC)

withlead used only insmall amounts inspecifically

exempted applications

• Integrated Memory Controller

– Low-latency, high-bandwidth

– 128-bit DDR2 SDRAM controller operating at up

to 333 MHz

– Supports up to two unbuffered SO-DIMMs

• Electrical Interfaces

– HyperTransport™ technology: LVDS-like

differential, unidirectional

– DDR2 SDRAM: SSTL_1.8 per JEDEC

specification

– Clock, reset, and test signals also use DDR2

SDRAM-like electrical specifications

• Power Management

– Multiple low-power states.

– System Management Mode (SMM)

– ACPI compliant, including support for processor

performance states.

– AMD PowerNow!™ technology is designed to

dynamically switch between multiple low-power

states based on application performance

requirements.

AMD Turion™ 64 Mobile Technology Product Data Sheet

32816 Rev. 3.05 September 2006

Revision History

Date Revision Description

September 2006 3.05 Third public release.

Added RoHS compliance statement for socket S1g1 processor-specific features.

August 2006 3.03 Second public release.

Updated Machine Check Architecture section.

June 2006 3.01 Initial public release.

The contents of this document are provided in connection with Advanced Micro Devices, Inc.

(“AMD”) products. AMD makes no representations or warranties with respect to the accuracy

or completeness of the contents of this publication and reserves the right to make changes to

specifications and product descriptions at any time without notice. The information contained

herein may be of a preliminary or advance nature and is subject to change without notice. No

license, whether express, implied, arising by estoppel or otherwise, to any intellectual

property rights is granted by this publication. Except as set forth in AMD’s Standard Terms

and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or

implied warranty, relating to its products including, but not limited to, the implied warranty of

merchantability, fitness for a particular purpose, or infringement of any intellectual property

right.

AMD’s products are not designed, intended, authorized or warranted for use as components in

systems intended for surgical implant into the body, or in other applications intended to

support or sustain life, or in any other application in which the failure of AMD’s product could

create a situation where personal injury, death, or severe property or environmental damage

may occur. AMD reserves the right to discontinue or make changes to its products at any time

without notice.

Trademarks

AMD, the AMD Arrow logo, AMD Turion and combinations thereof, 3DNow!, and AMD PowerNow! are trademarks of Advanced

Micro Devices, Inc.

HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.

MMX is a trademark of Intel Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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