Atmel AT24C16C Manuale utente

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

Standard Features

Low-voltage and Standard-voltage Operation

VCC = 1.7V to 5.5V

Internally Organized as 2,048 x 8 (16K)

I2C-compatible (2-wire) Serial Interface

Schmitt Trigger, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

1MHz (2.5V, 2.7V, 5V), 400kHz (1.7V) Compatibility

Write Protect Pin for Hardware Data Protection

16-byte Page Write Mode

Partial Page Writes Allowed

Self-timed Write Cycle (5ms Max)

High-reliability

Endurance: 1,000,000 Write Cycles

Data Retention: 100 Years

Green Package Options (Pb/Halide-free/RoHS Compliant)

8-lead PDIP, 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN,

5-lead SOT23, and 8-ball VFBGA

Die Options: Wafer Form and Tape and Reel

Description

The Atmel®AT24C16C provides 16,384 bits of Serial Electrically Erasable and

Programmable Read-Only Memory (EEPROM) organized as 2,048 words of 8 bits

each. The device is optimized for use in many industrial and commercial

applications where low-power and low-voltage operation are essential.

AT24C16C is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead

TSSOP, 8-pad UDFN,8-pad XDFN, 5-lead SOT23, and 8-ball VFBGA packages

and is accessed via a 2-wire serial interface.

AT24C16C

I2C-Compatible, (2-Wire) Serial EEPROM

16-Kbit (2048 x 8)

DATASHEET

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

1. Pin Configurations and Pinouts

Table 1. Pin Configuration

2. Absolute Maximum Ratings

Pin Name Function

NC No Connect

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

GND Ground

VCC Power Supply

GND

VCC

SCL

SDA

8-lead PDIP

SCL

GND

SDA

VCC

5-lead SOT23

VCC

SCL

SDA

GND

8-ball VFBGA

Bottom View

Note: Drawings are not to scale.

8-pad UDFN/XDFN

Bottom View

Top ViewTop View

Top View

VCC

SCL

SDA

GND

8-lead TSSOP

GND

VCC

SCL

SDA

8-lead SOIC

GND

VCC

SCL

SDA

Operating Temperature . . . . . . . . . . .-55C to +125C

Storage Temperature . . . . . . . . . . . . .-65C to +150C

Voltage on any pin

with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V

Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V

DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA

*Notice: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

3. Block Diagram

4. Pin Description

Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative

edge clock data out of each device.

Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may

be wire-ORed with any number of other open-drain or open-collector devices.

Device/Page Addresses: The AT24C16C does not use the device address pins, which limits the number of

devices on a single bus to one (see Section 7. “Device Addressing” on page 9).

Write Protect (WP): AT24C16C has a Write Protect pin that provides hardware data protection. The Write

Protect pin allows normal Read/Write operations when connected to Ground (GND). When the Write Protect pin

is connected to VCC, the Write Protection feature is enabled and operates as shown in Table 4-1.

Table 4-1. Write Protect

Start

Stop

Logic

Data Word

ADDR/Counter

Row Decoder

Device

Address

Comparator

Data Latches

OUT

/ ACK

Logic

Column

Decoder

EEPROM

Array

Serial

Control

Logic

High Voltage

Pump & Timing

Serial MUX

Read/Write

Enable

COMP Load

INC

GND

SCL

SDA

OUT

WP Pin Status Part of the Array Protected

At VCC Full Array

At GND Normal Read/Write Operations

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

5. Memory Organization

AT24C16C, 16K Serial EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires a

11-bit data word address for random word addressing.

5.1 Pin Capacitance

Table 5-1. Pin Capacitance(1)

Note: 1. This parameter is characterized and is not 100% tested.

5.2 DC Characteristics

Table 5-2. DC Characteristics

Note: 1. VIL min and VIH max are reference only and are not tested.

Applicable over recommended operating range from TA= 25°C, f = 1.0MHz, VCC = 5.5V.

Symbol Test Condition Max Units Conditions

CI/O Input/Output capacitance (SDA) 8 pF VI/O = 0V

CIN Input capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.7 5.5 V

ICC Supply Current VCC = 5.0V Read at 100kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V Write at 100kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 1.7V VIN = VCC or VSS 1.0 μA

ISB2 Standby Current VCC = 5.5V VIN = VCC or VSS 6.0 μA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 μA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 μA

VIL Input Low Level(1) –0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V

VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

5.3 AC Characteristics

Table 5-3. AC Characteristics

Note: 1. This parameter is ensured by characterization only.

Applicable over recommended operating range from TAI = -40C to 85C, VCC = +1.7V to 5.5V, CL = 1TTL Gate and 100pF

(unless otherwise noted).

Symbol Parameter

1.7V 2.5V, 2.7V, 5.0V

UnitsMin Max Min Max

fSCL Clock Frequency, SCL 400 1000 kHz

tLOW Clock Pulse Width Low 1.2 0.4 μs

tHIGH Clock Pulse Width High 0.6 0.4 μs

tINoise Suppression Time 100 50 ns

tAA Clock Low to Data Out Valid 0.1 0.9 0.05 0.55 μs

tBUF

Time the bus must be free before a new

transmission can start. 1.2 0.5 μs

tHD.STA Start Condition Hold Time 0.6 0.25 μs

tSU.STA Start Condition Setup Time 0.6 0.25 μs

tHD.DAT Data In Hold Time 0 0 μs

tSU.DAT Data In Setup Time 100 100 ns

tRInputs Rise Time(1) 0.3 0.3 μs

tFInputs Fall Time(1) 300 100 ns

tSU.STO Stop Condition Setup Time 0.6 .25 μs

tDH Data Out Hold Time 50 50 ns

tWR Write Cycle Time 5 5 ms

Endurance(1) 3.3V, 25C, Page Mode 1,000,000 Write Cycles

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

6. Device Operation

Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin

may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or

Stop Condition as defined below.

Figure 6-1. Data Validity

Start Condition: A high-to-low transition of SDA with SCL high is a Start Condition which must precede any

other command.

Stop Condition: A low-to-high transition of SDA with SCL high is a Stop Condition. After a read sequence, the

Stop Condition command will place the EEPROM in a standby power mode.

Figure 6-2. Start Condition and Stop Condition Definition

SDA

SCL

Data Stable Data Stable

Data

Change

SDA

SCL

Start

Condition

Stop

Condition

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in eight bit

words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the

ninth clock cycle.

Figure 6-3. Output Acknowledge

Standby Mode: The AT24C16C features a low-power standby mode which is enabled:

Upon power-up.

After the receipt of the Stop Condition and the completion of any internal operations.

2-wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be

reset by following these steps:

1. Create a Start Condition (if possible).

2. Clock nine cycles.

3. Create another Start Condition followed by Stop Condition as shown below.

The device should be ready for the next communication after above steps have been completed. In the event

that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset

the device.

Figure 6-4. Software Reset

SCL

DATA IN

DATA OUT

Start

Condition

Acknowledge

SCL 9

Start

Condition Start

Condition

Stop

Condition

8321

SDA

Dummy Clock Cycles

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

Figure 6-5. Bus Timing

SCL: Serial Clock, SDA: Serial Data I/O

Figure 6-6. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid Stop Condition of a Write sequence to the end of the internal

clear/write cycle.

SCL

SDA IN

SDA OUT

tHIGH

tLOW tLOW

tAA tDH tBUF

tSU.STO

tSU.DAT

tHD.DAT

tHD.STA

tSU.STA

tWR

(1)

Stop

Condition

Start

Condition

WORDn

ACK

8th bit

SCL

SDA

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

7. Device Addressing

Standard EEPROM Access: The 16K EEPROM device requires an 8-bit device address word following a Start

Condition to enable the chip for a Read or Write operation. The device address word consists of a mandatory

“1010” (Ah) sequence for the first four Most Significant Bits (MSB) as shown in Figure 10. on page 12. This is

common to all the EEPROM devices.

The next three bits used for memory page addressing are the most significant bits of the data word address

which follows.

The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit

is high and a Write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will

return to a standby state.

Figure 7-1. Device Address

8. Write Operations

Byte Write: A Write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in

the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the

addressing device, such as a microcontroller, must terminate the Write sequence with a Stop Condition. At this

time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled

during this write cycle and the EEPROM will not respond until the Write is complete.

Figure 8-1. Byte Write

Page Write: The 16K EEPROM devices are capable of a 16-byte Page Write.

A Page Write is initiated in the same way as a Byte Write, but the microcontroller does not send a Stop

Condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first

data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a

zero after each data word received. The microcontroller must terminate the Page Write sequence with a Stop

Condition (see Figure 8-2).

Density Access Area Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16K EEPROM 1 0 1 0 P2 P1 P0 R/W

MSB LSB

SDA Line

Device

Address Word Address Data

AT24C16C [DATASHEET]

Atmel-8719D-SEEPROM-AT24C16C-Datasheet_122016

The data word address lower four bits are internally incremented following the receipt of each data word. The

higher data word address bits are not incremented, retaining the memory page row location. When the word

address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the

same page. If more than eight data words are transmitted to the EEPROM, the data word address will roll-over

and previous data will be overwritten.

Figure 8-2. Page Write

Acknowledge Polling: Once the internally timed write cycle has started and the EEPROM inputs are disabled,

Acknowledge Polling can be initiated. This involves sending a Start Condition followed by the device address

word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has

completed will the EEPROM respond with a zero allowing the Read or Write sequence to continue.

9. Read Operations

Read operations are initiated in the same way as Write operations with the exception that the Read/Write select

bit in the device address word is set to one. There are three read operations:

Current Address Read

Random Address Read

Sequential Read.

Current Address Read: The internal data word address counter maintains the last address accessed during

the last Read or Write operation, incremented by one. This address stays valid between operations as long as

the chip power is maintained. The address roll-over during Read is from the last byte of the last memory page to

the first byte of the first page. The address roll-over during Write is from the last byte of the current page to the

first byte of the same page.

Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the

EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an

input zero but does generate a following Stop Condition (see Figure 9-1).

Figure 9-1. Current Address Read

SDA Line

Device

Address

Word

Address (n) Data (n) Data (n + 1) Data (n + x)

SDA Line

Device

Address Data

Indice

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