Atmel AT89C5130A-M Manuale utente

Features

•80C52X2 Core (6 Clocks per Instruction)

– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

– Dual Data Pointer

– Full-duplex Enhanced UART (EUART)

– Three 16-bit Timer/Counters: T0, T1 and T2

– 256 Bytes of Scratchpad RAM

•16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

•3-KbyteFlash EEPROM for Bootloader

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

•1-Kbyte EEPROM Data (

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

•On-chip Expanded RAM (ERAM): 1024 Bytes

•Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

•USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers: 32-byte FIFO

– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

• Endpoint 1, 2, 3: 32-byte FIFO

• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)

• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)

– Suspend/Resume Interrupts

– 48 MHz PLL for Full-speed Bus Operation

– Bus Disconnection on Microcontroller Request

•5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed

Output, Compare/Capture, PWM and Watchdog Timer Capabilities

•Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 100 ms

to 3s at 8 MHz

•Keyboard Interrupt Interface on Port P1 (8 Bits)

•TWI (Two Wire Interface) 400Kbit/s

•SPI Interface (Master/Slave Mode)

•34 I/O Pins

•4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical

•4-level Priority Interrupt System (11 sources)

•Idle and Power-down Modes

•0 to 24 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis

•Industrial Temperature Range

•Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB)

•Packages: PLCC52, VQFP64, QFN32

8-bit Flash

Microcontroller

with Full Speed

USB Device

AT89C5130A-M

AT89C5131A-M

BDTIC www.bdtic.com/ATMEL

4337K–USB–04/08

AT89C5130A/31A-M

1. Description

AT89C5130A/31A-M is a high-performance Flash version of the 80C51 single-chip 8-bit micro-

controllers with full speed USB functions.

AT89C5130A/31A-M features a full-speed USB module compatible with the USB specifications

Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V voltage regulator

and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recov-

ery. USB Event detection logic (Reset and Suspend/Resume) and FIFO buffers supporting the

m a n d a t o ry c o n t r o l E n d p oi n t ( E P 0 ) a n d up t o 6 v e r s a t i l e E n d po i n t s

(EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part of the USB

module.

AT89C5130A/31A-M retains the features of the Atmel 80C52 with extended Flash capacity

(16/32-Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters

(T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator.

In addition, AT89C5130A/31A-M has an on-chip expanded RAM of 1024 bytes (ERAM), a dual

data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA), up to 4 pro-

grammable LED current sources, a programmable hardware watchdog and a power-on reset.

AT89C5130A/31A-M has two software-selectable modes of reduced activity for further reduction

in power consumption. In the idle mode the CPU is frozen while the timers, the serial ports and

the interrupt system are still operating. In the power-down mode the RAM is saved, the periph-

eral clock is frozen, but the device has full wake-up capability through USB events or external

interrupts.

4337K–USB–04/08

AT89C5130A/31A-M

2. Block Diagram

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

3. Alternate function of Port 4

Timer 0 INT

RAM

256x8

RxD

TxD

PSEN

ALE

XTAL2

XTAL1

EUART

CPU

Timer 1

INT1

Ctrl

INT0

(2)

C51

CORE

(2) (2) (2) (2)

Port 0

Port 1 Port 2 Port 3

Parallel I/O Ports & Ext. Bus

ERAM

1Kx8

PCA

RST

Watch

Dog

CEX

ECI

VSS

VDD

(2)(2) (1)(1)

Timer2

T2EX

(1) (1)

Port 4

16/32Kx8Flash

BRG

USB

D -

D +

VREF

Regu-

Key

Board

KIN [0..7]

lator

AVSS

EEPROM

4Kx8

SPI

MISO

MOSI

SCK

(1) (1) (1)

(1)

AVDD

TWI

SCL

SDA

(3) (3)

4337K–USB–04/08

AT89C5130A/31A-M

3. Pinout Description

3.1 Pinout

Figure 3-1. AT89C5130A/31A-M 52-pin PLCC Pinout

21 22 26252423 292827 30 31

5 4 3 2 16 52 51 50 49 48

PLCC52

7 47

20 32 33

P1.1/T2EX/KIN1/SS

P1.0/T2/KIN0

P0.6/AD6

ALE

P0.7/AD7

PSEN

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

PLLF

P3.0/RxD

AVSS

P2.6/A14

XTAL1

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

VREF

P0.2/AD2

P0.0/AD0

P0.1/AD1

AVDD

UCAP

P3.2/INT0

P3.6/WR/LED2

XTAL2

RST

P3.1/TxD

P3.3/INT1/LED0

P3.7/RD/LED3

D-

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

VSS

P2.4/A12

P4.1/SDA

D+

P4.0/SCL

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P3.4/T0

P3.5/T1/LED1

VDD

UVSS

P2.7/A15

4337K–USB–04/08

AT89C5130A/31A-M

Figure 3-2. AT89C5130A/31A-M 64-pin VQFP Pinout

17 18 22212019 252423 26 27

62 61 60 59 5863 57 56 55 54 53

VQFP64

64 52

28 29

51 50 49

3132

P1.1/T2EX/KIN1/SS

ALE

PSEN

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P2.7/A15

P2.6/A14

P4.1/SDA

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P1.0/T2/KIN0

PLLF

UCAP

XTAL2 RST

P3.7/RD/LED3

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P3.0/RxD

VREF

P0.0/AD0

AVSS

P3.2/INT0

P3.6/WR/LED2

P3.1/TxD

P3.3/INT1/LED0

VSS

P3.4/T0

P3.5/T1/LED1

P0.6/AD6

P0.7/AD7

P2.5/A13

P0.3/AD3

P0.5/AD5

P0.4/AD4

P0.2/AD2

P0.1/AD1

D-

D+

P4.0/SCL

XTAL1

AVDD

UVSS

VDD

4337K–USB–04/08

AT89C5130A/31A-M

Figure 3-3. AT89C5130A/31A-M 32-pin QFN Pinout

3.2 Signals

All the AT89C5130A/31A-M signals are detailed by functionality on Table 3-1 through Table 3-

12.

Table 3-1. Keypad Interface Signal Description

Table 3-2. Programmable Counter Array Signal Description

QFN32

P1.1/T2EX/KIN1/SS

P1.7/CEX4/KIN7/MOSI

P1.3/CEX0/KIN3

P1.5/CEX2/KIN5/MISO

P1.6/CEX3/KIN6/SCK

P3.0/RxD

AVSS

XTAL1

VREF

UCAP

P3.2/INT0

P3.5/T1/LED1

XTAL2 RST

P3.1/TxD

P3.3/INT1/LED0

P3.7/RD/LED3

D-

VSS

P4.1/SDA

D+

P4.0/SCL

P1.2/ECI/KIN2

P1.4/CEX1/KIN4

P3.4/T0

P1.0/T2/KIN0

VDD

PLLF

P3.6/WR/LED2

UVSS

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

Note : The metal plate can be connected to Vss

Signal

Name Type Description

Alternate

Function

KIN[7:0) I

Keypad Input Lines

Holding one of these pins high or low for 24 oscillator periods triggers a

keypad interrupt if enabled. Held line is reported in the KBCON register.

P1[7:0]

Signal

Name Type Description

Alternate

Function

ECI I External Clock Input P1.2

4337K–USB–04/08

AT89C5130A/31A-M

Table 3-3. Serial I/O Signal Description

CEX[4:0] I/O

Capture External Input

Compare External Output

P1.3

P1.4

P1.5

P1.6

P1.7

Signal

Name Type Description

Alternate

Function

RxD I Serial Input Port P3.0

TxD O Serial Output Port P3.1

Table 3-4. Timer 0, Timer 1 and Timer 2 Signal Description

Signal

Name Type Description

Alternate

Function

INT0 I

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by GATE0

bit in TCON register.

External Interrupt 0

INT0 input set IE0 in the TCON register. If bit IT0 in this register is set, bits

IE0 are set by a falling edge on INT0. If bit IT0 is cleared, bits IE0 is set by

a low level on INT0.

P3.2

INT1 I

Timer 1 Gate Input

INT1 serves as external run control for Timer 1, when selected by GATE1

bit in TCON register.

External Interrupt 1

INT1 input set IE1 in the TCON register. If bit IT1 in this register is set, bits

IE1 are set by a falling edge on INT1. If bit IT1 is cleared, bits IE1 is set by

a low level on INT1.

P3.3

T0 I

Timer Counter 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin

increments the count.

P3.4

T1 I

Timer/Counter 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin

increments the count.

P3.5

T2 I

Timer/Counter 2 External Clock Input

Timer/Counter 2 Clock Output P1.0

T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input P1.1

Signal

Name Type Description

Alternate

Function

4337K–USB–04/08

AT89C5130A/31A-M

Table 3-5. LED Signal Description

Table 3-6. TWI Signal Description

Table 3-7. SPI Signal Description

Signal

Name Type Description

Alternate

Function

LED[3:0] O

Direct Drive LED Output

These pins can be directly connected to the Cathode of standard LEDs

without external current limiting resistors. The typical current of each

output can be programmed by software to 2, 6 or 10 mA. Several outputs

can be connected together to get higher drive capabilities.

P3.3

P3.5

P3.6

P3.7

Signal

Name Type Description

Alternate

Function

SCL I/O

SCL: TWI Serial Clock

SCL output the serial clock to slave peripherals.

SCL input the serial clock from master.

P4.0

SDA I/O SDA: TWI Serial Data

SCL is the bidirectional TWI data line. P4.1

Signal

Name Type Description

Alternate

Function

SS I/O SS: SPI Slave Select P1.1

MISO I/O

MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave

peripheral. When SPI is in slave mode, MISO outputs data to the master

controller.

P1.5

SCK I/O SCK: SPI Serial Clock

SCK outputs clock to the slave peripheral or receive clock from the master P1.6

MOSI I/O MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral.

When SPI is in slave mode, MOSI receives data from the master controller

P1.7

4337K–USB–04/08

AT89C5130A/31A-M

Table 3-8. Ports Signal Description

Table 3-9. Clock Signal Description

Signal

Name Type Description Alternate Function

P0[7:0] I/O

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0

pins that have 1s written to them float and can be used

as high impedance inputs. To avoid any parasitic current

consumption, Floating P0 inputs must be pulled to VDD or

VSS.

AD[7:0]

P1[7:0] I/O Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

KIN[7:0]

T2EX

ECI

CEX[4:0]

P2[7:0] I/O Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups. A[15:8]

P3[7:0] I/O Port 3

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

LED[3:0]

RxD

TxD

INT0

INT1

P4[1:0] I/O Port 4

P4 is an 2-bit open drain port.

SCL

SDA

Signal

Name Type Description

Alternate

Function

XTAL1 I

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this

pin. If an external oscillator is used, its output is connected to this pin.

XTAL2 O

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this

pin. If an external oscillator is used, leave XTAL2 unconnected.

PLLF I PLL Low Pass Filter input

Receive the RC network of the PLL low pass filter. -

4337K–USB–04/08

AT89C5130A/31A-M

Table 3-10. USB Signal Description

Table 3-11. System Signal Description

Signal

Name Type Description

Alternate

Function

D+ I/O USB Data + signal

Set to high level under reset. -

D- I/O USB Data - signal

Set to low level under reset. -

VREF O USB Reference Voltage

Connect this pin to D+ using a 1.5 kΩresistor to use the Detach function. -

Signal

Name Type Description

Alternate

Function

AD[7:0] I/O Multiplexed Address/Data LSB for external access

Data LSB for Slave port access (used for 8-bit and 16-bit modes) P0[7:0]

A[15:8] I/O Address Bus MSB for external access P2[7:0]

RD I/O

Read Signal

Read signal asserted during external data memory read operation.

Control input for slave port read access cycles.

P3.7

WR I/O

Write Signal

Write signal asserted during external data memory write operation.

Control input for slave write access cycles.

P3.6

RST O

Reset Input

Holding this pin low for 64 oscillator periods while the oscillator is running

resets the device. The Port pins are driven to their reset conditions when a

voltage lower than VIL is applied, whether or not the oscillator is running.

This pin has an internal pull-up resistor which allows the device to be reset

by connecting a capacitor between this pin and VSS.

Asserting RST when the chip is in Idle mode or Power-down mode returns

the chip to normal operation.

This pin is tied to 0 for at least 12 oscillator periods when an internal reset

occurs ( hardware watchdog or power monitor).

ALE O

Address Latch Enable Output

The falling edge of ALE strobes the address into external latch. This signal

is active only when reading or writing external memory using MOVX

instructions.

PSEN I/O

Program Strobe Enable / Hardware conditions Input for ISP

Used as input under reset to detect external hardware conditions of ISP

mode.

EA I

External Access Enable

This pin must be held low to force the device to fetch code from external

program memory starting at address 0000h.

Table 3-12. Power Signal Description

Signal

Name Type Description

Alternate

Function

AVSS GND Analog Ground

AVSS is used to supply the on-chip PLL and the USB PAD. -

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