Atmel AT90S2313 Manuale utente

Features

•Utilizes the AVR®RISC Architecture

•AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 10 MIPS Throughput at 10 MHz

•Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles

– 128 Bytes of SRAM

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Flash Program and EEPROM Data Security

•Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler

– One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9- or 10-bit PWM

– On-chip Analog Comparator

– Programmable Watchdog Timer with On-chip Oscillator

– SPI Serial Interface for In-System Programming

– Full Duplex UART

•• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

•• Specifications

– Low-power, High-speed CMOS Process Technology

– Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.8 mA

– Idle Mode: 0.8 mA

– Power-down Mode: <1 µA

•I/O and Packages

– 15 Programmable I/O Lines

– 20-pin PDIP and SOIC

•Operating Voltages

– 2.7 - 6.0V (AT90S2313-4)

– 4.0 - 6.0V (AT90S2313-10)

•Speed Grades

– 0 - 4 MHz (AT90S2313-4)

– 0 - 10 MHz (AT90S2313-10)

Rev. 0839G–08/01

8-bit

Microcontroller

with 2K Bytes

of In-System

Programmable

Flash

AT90S2313

Pin Configuration

PDIP/SOIC

2AT90S2313

0839G–08/01

Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S2313

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general-purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),

allowing two independent registers to be accessed in one single instruction executed in

one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

Figure 1. The AT90S2313 Block Diagram

The AT90S2313 provides the following features: 2K bytes of In-System Programmable

Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general-purpose I/O lines, 32 general-

purpose working registers, flexible timer/counters with compare modes, internal and

external interrupts, a programmable serial UART, programmable Watchdog Timer with

internal oscillator, an SPI serial port for Flash memory downloading and two software

AT90S2313

0839G–08/01

selectable power-saving modes. The Idle Mode stops the CPU while allowing the

SRAM, timer/counters, SPI port and interrupt system to continue functioning. The

Power-down Mode saves the register contents but freezes the oscillator, disabling all

other chip functions until the next external interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

The on-chip In-System Programmable Flash allows the program memory to be repro-

grammed in-system through an SPI serial interface or by a conventional nonvolatile

memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-

grammable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful

microcontroller that provides a highly flexible and cost-effective solution to many embed-

ded control applications.

The AT90S2313 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators and evaluation kits.

Pin Descriptions

VCC Supply voltage pin.

GND Ground pin.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the

negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output

buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7 are

used as inputs and are externally pulled low, they will source current if the internal pull-

up resistors are activated. The Port B pins are tri-stated when a reset condition

becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S2313 as listed

on page 53.

Port D (PD6..PD0) Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The

Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled

low will source current if the pull-up resistors are activated. The Port D pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Port D also serves the functions of various special features of the AT90S2313 as listed

on page 58.

RESET Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the

clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

4AT90S2313

0839G–08/01

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can

be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz

crystal or a ceramic resonator may be used. To drive the device from an external clock

source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3.

Figure 2. Oscillator Connections

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be

connected as indicated in the figure.

Figure 3. External Clock Drive Configuration

XTAL2

XTAL1

GND

MAX 1 HC BUFFER

AT90S2313

0839G–08/01

Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed, and the result is stored back in the register

file – in one clock cycle.

Figure 4. The AT90S2313 AVR RISC Architecture

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the three

address pointers is also used as the address pointer for the constant table look-up func-

tion. These added function registers are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the AT90S2313 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be

used on the register file as well. This is enabled by the fact that the register file is

assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be

accessed as though they were ordinary memory locations.

6AT90S2313

0839G–08/01

The I/O memory space contains 64 addresses for CPU peripheral functions such as

control registers, timer/counters, A/D converters and other I/O functions. The I/O mem-

ory can be accessed directly or as the Data Space locations following those of the

The AVR has Harvard architecture – with separate memories and buses for program

and data. The program memory is accessed with a 2-stage pipeline. While one instruc-

tion is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program

memory is In-System Programmable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the stack. The stack is effectively allocated in the general data SRAM, and

consequently the stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The 8-bit stack pointer (SP) is read/write accessible in the

I/O space.

The 128 bytes data SRAM + register file and I/O registers can be easily accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

AT90S2313

0839G–08/01

Figure 5. Memory Maps

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the Status Register. All the different interrupts have a sepa-

rate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt

vector position. The lower the interrupt vector address, the higher the priority.

8AT90S2313

0839G–08/01

General-purpose

Figure 6 shows the structure of the 32 general-purpose registers in the CPU.

Figure 6. AVR CPU General-purpose Working Registers

All the register operating instructions in the instruction set have direct and single-cycle

access to all registers. The only exception is the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI

instruction for load immediate constant data. These instructions apply to the second half

of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR and

all other operations between two registers or on a single register apply to the entire reg-

ister file.

As shown in Figure 6, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although the register file

is not physically implemented as SRAM locations, this memory organization provides

great flexibility in access of the registers, as the X, Y and Z registers can be set to index

any register in the file.

X-register, Y-register, and Z-

The registers R26..R31 have some added functions to their general-purpose usage.

These registers are the address pointers for indirect addressing of the Data Space. The

three indirect address registers X, Y and Z are defined in Figure 7.

Figure 7. X, Y and Z Registers

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

AT90S2313

0839G–08/01

In the different addressing modes these address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories – arithmetic, logical and bit functions.

In-System

Programmable Flash

Program Memory

The AT90S2313 contains 2K bytes on-chip In-System Programmable Flash memory for

program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as

1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles.

The AT90S2313 Program Counter (PC) is 10 bits wide, thus addressing the 1,024 pro-

gram memory addresses.

See page 62 for a detailed description on Flash data downloading. See page 11 for the

different addressing modes.

EEPROM Data Memory The AT90S2313 contains 128 bytes of EEPROM data memory. It is organized as a sep-

arate data space in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM

and the CPU is described on page 40, specifying the EEPROM address register, the

EEPROM data register and the EEPROM control register.

For the SPI data downloading, see page 69 for a detailed description.

10 AT90S2313

0839G–08/01

SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized.

Figure 8. SRAM Organization

The 224 data memory locations address the Register file, I/O memory and the data

SRAM. The first 96 locations address the Register File + I/O Memory, and the next 128

locations address the data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the

The Direct addressing reaches the entire data address space.

The Indirect with Displacement mode features 63 address locations reached from the

base address given by the Y and Z registers.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y and Z are used and decremented and

incremented.

The 32 general-purpose working registers, 64 I/O registers and the 128 bytes of data

SRAM in the AT90S2313 are all directly accessible through all these addressing modes.

R0 $00

R1 $01

R2 $02

……

R29 $1D

R30 $1E

R31 $1F

I/O Registers

$00 $20

$01 $21

$02 $22

……

$3D $5D

$3E $5E

$3F $5F

Internal SRAM

$60

$61

$62

…

$DD

$DE

$DF

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