Cirrus Logic CDB43131-GBK Manuale utente

CDB43131-GBK

CDB43131-GBK Kit Manual

http://www.cirrus.com

Cirrus Logic International Semiconductor Ltd.

DS1155V2DB1

JUL '18

Features

•Configurable serial audio headers for PCM, DSD and DoP audio

•Headphone and line outputs

•Analog and S/PDIF audio input

•USB audio module capability

•WISCE™ I2C-based software control

•Windows® compatible

Description

The CDB43131-GBK is a dedicated platform for testing and evaluating the CS43131. The CS43131 is a high-performance

audio DAC with integrated impedance detection and headphone drivers. To allow comprehensive testing and evaluation

of the performance of the CS43131, extensive software-configurable options are available through the CDB43131

evaluation kit. The kit also included the CDB-HDR-MEAS, for measuring the 130 dB dynamic range performance of the

CS43131.

Software options, such as register settings for the CS43131, are configured via the WISCE software tool, which

communicates with the CDB43131-GBK via an Aardvark I2C/SPI host adapter from a Windows computer, or via Mini-USB

cable.

Figure 1 CDB43131 Board Block Diagram

 CDB43131-GBK 
 
2DS1155V2DB1 
Table of Contents 
1CDB43131-GBK Kit Overview ........................................................................................................................................3 
1.1 CDB43131 Board..........................................................................................................................................................3 
1.2 CDB-HDR-MEAS Board...............................................................................................................................................3 
2CDB43131 Board Overview............................................................................................................................................4 
2.1 Power Supply Circuitry .................................................................................................................................................5 
2.2 Digital Audio Input.........................................................................................................................................................6 
2.3 Analog Audio Input .......................................................................................................................................................9 
2.4 Analog Audio Output................................................................................................................................................... 10 
2.5 I2C Control ..................................................................................................................................................................10 
2.6 LEDs...........................................................................................................................................................................11 
2.7 List of Headers and Jumper Settings .........................................................................................................................12 
2.8 Codec MCLK Selection...............................................................................................................................................14 
2.9 Clock Sources.............................................................................................................................................................14 
3Board Control Register Quick Reference................................................................................................................... 15 
3.1 Register Descriptions..................................................................................................................................................15 
4CDB-HDR-MEAS High Dynamic Range Measurement Preamplifier........................................................................ 19 
4.1 Powering the CDB-HDR-MEAS..................................................................................................................................19 
4.2 How the CDB-HDR-MEAS Works..............................................................................................................................20 
5Testing the CS43131 using WISCE Software.............................................................................................................21 
5.1 Launching WISCE Software.......................................................................................................................................21 
5.2 Loading the CDB43131 board Panel and Register Map............................................................................................22 
5.3 Loading the CS43131 Plugins and Register Map.......................................................................................................24 
5.4 Initializing the Devices on the CDB43131 Board........................................................................................................26 
5.5 CS43131 Plugin..........................................................................................................................................................27 
6Testing Various Use cases .......................................................................................................................................... 44 
6.1 Data Flow for Various Use Cases ..............................................................................................................................45 
6.2 Measuring Dynamic Range and THD+N for the CS43131.........................................................................................48 
6.3 Measured Results.......................................................................................................................................................58 
7Revision History............................................................................................................................................................ 59 
 
 
 

CDB43131-GBK

DS1155V2DB1 3

1 CDB43131-GBK Kit Overview

The CDB43131-GBK kit consists of an evaluation board, a high dynamic range (HDR) measurement board, and a USB

cable. Each of these component boards is described in the following sections.

1.1 CDB43131 Board

The CDB43131 is shown in the following figure.

Figure 2 CDB43131 Base Board

1.2 CDB-HDR-MEAS Board

The CDB-HDR-MEAS is shown in the following figure. This board is used for measuring the very low HDR of the device

with an Audio Precision SYS-2700 or APx555 audio analyzer.

Figure 3 CDB-HDR-MEAS Board

CDB43131-GBK

4DS1155V2DB1

2 CDB43131 Board Overview

The CDB43131 is the board for evaluating the performance of the CS43131. It supports multiple power supplies and

signal I/O configurations.

The CDB43131 board uses five buffers with direction control to direct clock from the digital input sources to/from the

CS43131 DUTs. Two buffers, the PCM/DoP buffer and the DSD/DoP buffer, support voltage translation from 3.3 V to 1.8

V and vice versa. The voltage selection is done through headers: J28 for the PCM/DoP buffer and the DSD/DoP buffer.

The S/PDIF buffer is a unidirectional buffer and supports 3.3 V to 1.8 V translation. The remaining buffers only support 1.8

V signals. These buffers are controlled by an I/O Expander. The I/O Expander can be controlled through its I2C interface.

The register map for I/O Expander is described in Section 3. The direction of clock signals is determined by the

CS43131’s operating mode (master or slave mode).

The CDB43131 can also communicate with a smart codec through the use of J42. The purpose of using a smart codec is

to allow the user to perform listening tests with various equalizer (EQ) filters based on the impedance of the attached

headphone. The CDB43131 board allows the PCM input to be routed to the smart codec. The codec can then apply an

EQ filter on this data, based on the impedance of the attached headphone and send EQ-filtered data to the CS43131, for

an optimal listening experience. The following diagram shows an overview of the CDB43131 board.

Figure 4 CDB43131 Block Diagram

CDB43131-GBK

DS1155V2DB1 5

2.1 Power Supply Circuitry

The CDB43131 board is powered from a 5-volt, 1.2-amp AC adapter or via the +5-volt bus from the USB connector. All

the supply rails for both the smart codec and the CS43131s are generated using a combination of switched-mode power

supplies (switchers) and LDOs. In addition to these internal supplies, the CDB43131 board also provides the option of

powering the CS43131 supply rails from external bench supplies via banana jacks.

The switchers and LDOs step down the +5 V supply to 3.6 V, 3.3 V, 1.0 V, 1.8 V (analog), and 1.8 V (digital) levels.

If the device is set into External VCP_FILT Supply Mode and bypass the internal Class-H charge pump circuit, then a ±3-

volt supply must be applied to VCP_FILT+ and VCP_FILT-. The banana jacks are connected to each device through a set

of resistors (R24/R25 for the CSP device, and R40/R41 for the QFN device). These resistors are unpopulated by default

and will need to be populated with a 0-Ω resistor to connect the jack to the DUT.

Figure 5 CDB43131 Power Supplies

CDB43131-GBK

6DS1155V2DB1

2.2 Digital Audio Input

2.2.1 Serial Audio I/O Headers

Headers J25 and J26, labeled ASP and XSP respectively, provide an interface for serial audio clocks and data. The

source of the clocks and data can be an external audio source such as an Audio Precision audio analyzer. The header

signals are described in the table below. The logic level on these pins is selectable by jumping J28 to 3.3 V or 1.8V.

Table 1 Serial Audio Header Pinout

Reference Designator

Pins

Pin Designation

Direction

Description

J25

MCLK

I/O

Master clock

SCLK

I/O

Bit clock

LRCLK

I/O

Frame clock

RXDAT

Input

Serial data

2,4,6,8

Ground

Ground reference

Board ground

J26

MCLK

I/O

Master clock

SCLK

I/O

Bit clock

LRCLK

I/O

Frame clock

RXDAT

Input

Serial data

2,4,6,8

Ground

Ground reference

Board ground

Audio signals to/from these headers are routed to/from the CS43131 using voltage-level translation buffers. The direction

of clock and data through these buffers is controlled using on-board TCA6424 I/O Expander IC. U9, U12, and U15

translate the signals on J25 and J26 from a voltage of 3.3 V or 1.8 V to the operational voltage of 1.8 V. The ASP signals

are then fed into J24, while the XSP signals are fed into J44. These 3x3 pin headers are for passing the I2S data from the

CS8422 S/PDIF transceiver to the DUTs.

To avoid the latency caused by buffers for higher clock frequencies like 352.8 kHz or 384 kHz, the user can connect the

external audio source directly to pins on headers J24 and J44. The pinouts for headers J24 and J44 are shown in the

following tables.

Table 2 Pinouts for Header J24

Pin #

Signal

SCLK1 from Buffer

SCLK1 to DAC

LRCLK1 from Buffer

LRCLK1 to DAC

SDIN1 from Buffer

SDIN1 to DAC

3,6,9

Ground

Table 3 Pinouts for Header J44

Pin #

Signal

SCLK2 from Buffer

SCLK2 to DAC

LRCLK2 from Buffer

LRCLK2 to DAC

SDIN2 from Buffer

SDIN2 to DAC

3,6,9

Ground

CDB43131-GBK

DS1155V2DB1 7

To source the signals from the output of the buffers to the DAC, place jumpers between the two columns of pins labeled

BRD and DUT. For example, in order to send SCLK1, LRCLK1 and SDIN1 signals from the buffer to the DAC, place

jumpers between pins of the BRD and DUT group as shown in the following figure.

Figure 6 Jumper Settings to Route Signals from Buffers to DUT

CDB43131-GBK

8DS1155V2DB1

To source the signals from external audio source like an Audio Precision APx555, connect the cable that fits onto a 2-pin

header onto the pins labeled DUT and GND. For example, in order to send SCLK1, LRCLK1 and SDIN1 signals from an

APx to the DAC, connect the BITCLK output from the APx to the SCLK1 pins in the AP group, Frame CLK output from the

APx to LRCLK1 pins in the AP group, and the RXDAT1 output from the APx to SDIN1 pins in the AP group as shown in

the following figure.

Figure 7 External Audio Source to DUT

2.2.2 S/PDIF Receiver

The CS8422 S/PDIF receiver provides two-channel digital input either from an optical or coax connector. The CS8422 can

support sample rates up to 211 kHz and data output with either 16-, 18-, 20-, or 24-bit word lengths. Make sure that only

one source, either S/PDIF or coax, is used at one time to provide the input. The CS8422 is configured to operate in

Hardware Mode.

CDB43131-GBK

DS1155V2DB1 9

2.3 Analog Audio Input

The CDB43131 features a 1/8" headphone jack for each the CSP (J16) and QFN (J34). Situated next to each headphone

jack are a pair of testpoints (J18/J19 and J35/J36, respectively) for connecting to an APx.

Figure 8 1/8" Headphone Jack and APx connectors for CSP

Figure 9 1/8" Headphone Jack and APx connectors for QFN

CDB43131-GBK

10 DS1155V2DB1

2.4 Analog Audio Output

The CDB43131 board has one 1/8" stereo headphone output jack (J1) for the CSP and one XLR cable output jack (J60)

for the QFN.

Figure 10 1/8" Headphone Jack/APx Connectors/Loading Jumpers for CSP

Figure 11 XLR Output/APx Connectors/Loading Jumpers for QFN

2.5 I2C Control

Header J42 (labeled I2C/SPI) provides an interface to connect a Total Phase Aardvark I2C/SPI Host Adapter. The header

signals are described in the following table. The logic level on these pins is 3.3 V. Through this header, a user can

communicate with a smart codec, the TCA6424 I/O Expander, and the CS43131.

Table 4 I2C/SPI Header Pinout

Header

Pins

Designation

Description

J42

I2C_SCL

I2C clock

I2C_SDA

I2C data

SPI_MISO

SPI master in slave out

SPI_SCLK

SPI clock

SPI_SS

SPI chip select

SPI_MOSI

SPI master out slave in

2, 10

GND

Ground reference

4, 6

No connect

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