Cirrus Logic CS42518-CQ Manuale utente

Preliminary Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc.

http://www.cirrus.com

CS42518

110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

Features

Eight 24-bit D/A, two 24-bit A/D Converters

110 dB DAC / 114 dB ADC Dynamic Range

-100 dB THD+N

System Sampling Rates up to 192 kHz

S/PDIF Receiver compatible with EIAJ

CP1201 and IEC-60958

Recovered S/PDIF CLK or System Clock

Selection

8:2 S/PDIF Input MUX

ADC High Pass Filter for DC Offset

Calibration

Expandable ADC Channels and One-line-

Mode Support

Digital Output Volume control with soft ramp

Digital +/-15dB Input Gain Adjust for ADC

Differential Analog Architecture

Supports logic levels between 5 V and 1.8 V

General Description

The CS42518 codec provides two analog-to-digital and eight

digital-to-analog delta-sigma converters, as well as an integrat-

ed S/PDIF receiver, in a 64-pin LQFP package.

The CS42518 integrated S/PDIF receiver supports up to eight

inputs, clock recovery circuitry and format auto-detection. The

internal stereo ADC is capable of independent channel gain

control for single-ended or differential analog inputs. All eight

channels of DAC provide digital volume control and differential

analog outputs. The general purpose outputs may be driven

high or low, or mapped to a variety of DAC mute controls or

ADC overflow indicators.

The CS42518 is ideal for audio systems requiring wide dynam-

ic range, negligible distortion and low noise, such as A/V

receivers, DVD receivers, digital speaker and automotive audio

systems.

ORDERING INFORMATION

CS42518-CQ*

-10° to 70° C 64-pin LQFP

CS42518-DQ*

-40° to 85° C 64-pin LQFP

CDB42518

Evaluation Board

*Also available in Lead-Free package

RST

RXP0

RXP1/GPO1

AD0/CS

SCL/CCLK

SDA/CDOUT

AD1/CDIN

VLC

AOUTA1+

AOUTA1-

AOUTB1+

AOUTA3+

AOUTA3-

AOUTA2-

AOUTB2-

AOUTA2+

AOUTB2+

AOUTB1-

AOUTB3+

AOUTB3-

AOUTA4+

AOUTA4-

AOUTB4+

AOUTB4-

AINL+

AINL-

AINR+

AINR-

FILT+

REFGND

VQ Ref

ADC#1

ADC#2

Digital Filter

Gain & Clip

Gain & Clip CX_SDOUT

ADCIN1

ADCIN2

CX_SCLK

CX_LRCK

CX_SDIN4

CX_SDIN3

CX_SDIN2

CX_SDIN1

VLS

SAI_LRCK

SAI_SCLK

SAI_SDOUT

DGND VD

OMCK

RMCK

LPFLT

TXP

INT

Rx Clock/Data

Recovery S/PDIF

Decoder

DEM Serial

Audio

Interface

Port

C&U Bit

Data Buffer Control

Port

DAC#1

DAC#2

DAC#3

DAC#4

DAC#5

DAC#6

DAC#7

DAC#8

DigitalFilter

VolumeControl

DGND

RXP2/GPO2

RXP3/GPO3

RXP4/GPO4

RXP5/GPO5

RXP6/GPO6

RXP7/GPO7

MUTEC

GPO

MUTE

AnalogFilter

VARX AGND

ADC

Serial

Data

AGND

Internal MCLK

CODEC

Serial

Port

Mult/Div

Format

Detector

MAR ‘04

DS584PP3

CS42518

TABLE OF CONTENTS

1 CHARACTERISTICS AND SPECIFICATIONS .........................................................................6

SPECIFIED OPERATING CONDITIONS.................................................................................6

ABSOLUTE MAXIMUM RATINGS ...........................................................................................6

ANALOG INPUT CHARACTERISTICS....................................................................................7

A/D DIGITAL FILTER CHARACTERISTICS.............................................................................8

ANALOG OUTPUT CHARACTERISTICS................................................................................9

D/A DIGITAL FILTER CHARACTERISTICS...........................................................................10

SWITCHING CHARACTERISTICS ........................................................................................11

SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT................................12

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ...............................13

DC ELECTRICAL CHARACTERISTICS.................................................................................14

DIGITAL INTERFACE CHARACTERISTICS..........................................................................14

2 PIN DESCRIPTIONS ...............................................................................................................15

3 TYPICAL CONNECTION DIAGRAMS .................................................................................18

4 APPLICATIONS .......................................................................................................................20

4.1. Overview .........................................................................................................................20

4.2. Analog Inputs ..................................................................................................................20

4.2.1 Line Level Inputs .................................................................................................20

4.2.2 High Pass Filter and DC Offset Calibration .........................................................21

4.3. Analog Outputs ...............................................................................................................21

4.3.1 Line Level Outputs and Filtering .........................................................................21

4.3.2 Interpolation Filter ...............................................................................................21

4.3.3 Digital Volume and Mute Control ........................................................................22

4.3.4 ATAPI Specification ............................................................................................22

4.4. S/PDIF Receiver .............................................................................................................23

4.4.1 8:2 S/PDIF Input Multiplexer ...............................................................................23

4.4.2 Error Reporting and Hold Function .....................................................................23

4.4.3 Channel Status Data Handling ............................................................................23

4.4.4 User Data Handling .............................................................................................23

4.4.5 Non-Audio Auto-Detection ..................................................................................23

4.5. Clock Generation ............................................................................................................24

4.5.1 PLL and Jitter Attenuation ...................................................................................24

4.5.2 OMCK System Clock Mode ................................................................................25

4.5.3 Master Mode .......................................................................................................25

4.5.4 Slave Mode .........................................................................................................25

4.6. Digital Interfaces .............................................................................................................26

4.6.1 Serial Audio Interface Signals .............................................................................26

4.6.2 Serial Audio Interface Formats ............................................................................28

4.6.3 ADCIN1/ADCIN2 Serial Data Format ..................................................................31

4.6.4 One Line Mode(OLM) Configurations .................................................................32

4.6.4a OLM Config #1 .....................................................................................32

4.6.4b OLM Config #2 .....................................................................................33

4.6.4c OLM Config #3 .....................................................................................34

4.6.4d OLM Config #4 .....................................................................................35

4.6.4e OLM Config #5 .....................................................................................36

4.7. Control Port Description and Timing ...............................................................................37

4.7.1 SPI Mode ............................................................................................................37

4.7.2 I2C Mode .............................................................................................................38

4.8. Interrupts .........................................................................................................................39

4.9. Reset and Power-up ......................................................................................................39

4.10. Power Supply, Grounding, and PCB layout ..................................................................39

CS42518

5 REGISTER QUICK REFERENCE ........................................................................................... 41

6 REGISTER DESCRIPTION ..................................................................................................... 45

6.1 Memory Address Pointer (MAP)....................................................................................... 45

6.2 Chip I.D. and Revision Register (address 01h) (Read Only)............................................ 45

6.3 Power Control (address 02h)............................................................................................ 46

6.4 Functional Mode (address 03h)........................................................................................ 46

6.5 Interface Formats (address 04h) ...................................................................................... 48

6.6 Misc Control (address 05h) .............................................................................................. 50

6.7 Clock Control (address 06h)............................................................................................. 51

6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ......................................................... 53

6.9 RVCR Status (address 08h) (Read Only)......................................................................... 53

6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only).......................... 54

6.11 Volume Transition Control (address 0Dh) ...................................................................... 55

6.12 Channel Mute (address 0Eh).......................................................................................... 57

6.13 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) ........................ 57

6.14 Channel Invert (address 17h)......................................................................................... 57

6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)

Mixing Control Pair 2 (Channels A2 & B2)(address 19h)

Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)

Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) ............................................ 58

6.16 ADC Left Channel Gain (address 1Ch) .......................................................................... 60

6.17 ADC Right Channel Gain (address 1Dh)........................................................................ 60

6.18 Receiver Mode Control (address 1Eh) ........................................................................... 60

6.19 Receiver Mode Control 2 (address 1Fh) ........................................................................ 61

6.20 Interrupt Status (address 20h) (Read Only) ................................................................... 62

6.21 Interrupt Mask (address 21h) ......................................................................................... 63

6.22 Interrupt Mode MSB (address 22h)

Interrupt Mode LSB (address 23h)................................................................................ 63

6.23 Channel Status Data Buffer Control (address 24h)........................................................ 64

6.24 Receiver Channel Status (address 25h) (Read Only) .................................................... 64

6.25 Receiver Errors (address 26h) (Read Only)................................................................... 65

6.26 Receiver Errors Mask (address 27h).............................................................................. 67

6.27 MuteC Pin Control (address 28h)................................................................................... 67

6.28 RXP/General Purpose Pin Control (addresses 29h to 2Fh)........................................... 68

6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only)......................... 69

6.30 C-bit or U-bit Data Buffer (addresses 3Ah to 51h) (Read Only) ..................................... 69

7 PARAMETER DEFINITIONS ................................................................................................... 70

8 REFERENCES ......................................................................................................................... 71

9 PACKAGE DIMENSIONS .................................................................................................... 72

THERMAL CHARACTERISTICS ........................................................................................... 72

10 APPENDIX A: EXTERNAL FILTERS .................................................................................... 73

10.1. ADC Input Filter ............................................................................................................ 73

10.2. DAC Output Filter ......................................................................................................... 73

11 APPENDIX B: S/PDIF RECEIVER ........................................................................................ 74

11.1. Error Reporting and Hold Function ............................................................................... 74

11.2 Channel Status Data Handling ...................................................................................... 74

11.2.1 Channel Status Data E Buffer Access .............................................................. 75

11.2.1a One Byte mode .................................................................................. 75

11.2.1b Two Byte mode .................................................................................. 75

11.2.2 Serial Copy Management System (SCMS) ....................................................... 76

11.3. User (U) Data E Buffer Access ..................................................................................... 76

11.3.1 Non-Audio Auto-Detection ................................................................................ 76

11.3.1a Format Detection ............................................................................... 76

CS42518

12 APPENDIX C: PLL FILTER ...................................................................................................77

12.1. External Filter Components ..........................................................................................78

12.1.1 General .............................................................................................................78

12.1.2 Jitter Attenuation ...............................................................................................78

12.1.3 Capacitor Selection ...........................................................................................79

12.1.4 Circuit Board Layout ..........................................................................................79

13 APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ...............80

13.1. AES3 Receiver External Components ..........................................................................80

14 APPENDIX E: ADC FILTER PLOTS .....................................................................................81

15 APPENDIX F: DAC FILTER PLOTS .....................................................................................83

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing ..........................................................................11

Figure 2. Serial Audio Port Slave Mode Timing ............................................................................11

Figure 3. Control Port Timing - I2C Format...................................................................................12

Figure 4. Control Port Timing - SPI Format...................................................................................13

Figure 5. Typical Connection Diagram..........................................................................................18

Figure 6. Typical Connection Diagram with PLL...........................................................................19

Figure 7. Full-Scale Analog Input..................................................................................................20

Figure 8. Full-Scale Output ...........................................................................................................21

Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4).........................................................22

Figure 10. CS42518 Clock Generation .........................................................................................24

Figure 11. I2S Serial Audio Formats..............................................................................................28

Figure 12. Left Justified Serial Audio Formats ..............................................................................29

Figure 13. Right Justified Serial Audio Formats............................................................................29

Figure 14. One Line Mode #1 Serial Audio Format.......................................................................30

Figure 15. One Line Mode #2 Serial Audio Format.......................................................................30

Figure 16. ADCIN1/ADCIN2 Serial Audio Format.........................................................................31

Figure 17. OLM Configuration #1..................................................................................................32

Figure 18. OLM Configuration #2..................................................................................................33

Figure 19. OLM Configuration #3..................................................................................................34

Figure 20. OLM Configuration #4..................................................................................................35

Figure 21. OLM Configuration #5..................................................................................................36

Figure 22. Control Port Timing in SPI Mode..................................................................................37

Figure 23. Control Port Timing, I2C Write .....................................................................................38

Figure 24. Control Port Timing, I2C Read.....................................................................................38

Figure 25. Recommended Analog Input Buffer.............................................................................73

Figure 26. Recommended Analog Output Buffer ..........................................................................73

Figure 27. Channel Status Data Buffer Structure..........................................................................75

Figure 28. PLL Block Diagram ......................................................................................................77

Figure 29. Jitter Attenuation Characteristics of PLL......................................................................78

Figure 30. Recommended Layout Example..................................................................................79

Figure 31. Consumer Input Circuit ................................................................................................80

Figure 32. S/PDIF MUX Input Circuit ............................................................................................80

Figure 33. TTL/CMOS Input Circuit...............................................................................................80

Figure 34. Single Speed Mode Stopband Rejection .....................................................................81

Figure 35. Single Speed Mode Transition Band............................................................................81

Figure 36. Single Speed Mode Transition Band (Detail)...............................................................81

Figure 37. Single Speed Mode Passband Ripple..........................................................................81

Figure 38. Double Speed Mode Stopband Rejection....................................................................81

Figure 39. Double Speed Mode Transition Band..........................................................................81

Figure 40. Double Speed Mode Transition Band (Detail)..............................................................82

Figure 41. Double Speed Mode Passband Ripple........................................................................82

CS42518

Figure 42. Quad Speed Mode Stopband Rejection ...................................................................... 82

Figure 43. Quad Speed Mode Transition Band............................................................................. 82

Figure 44. Quad Speed Mode Transition Band (Detail)................................................................ 82

Figure 45. Quad Speed Mode Passband Ripple........................................................................... 82

Figure 46. Single Speed (fast) Stopband Rejection...................................................................... 83

Figure 47. Single Speed (fast) Transition Band............................................................................ 83

Figure 48. Single Speed (fast) Transition Band (detail)................................................................ 83

Figure 49. Single Speed (fast) Passband Ripple.......................................................................... 83

Figure 50. Single Speed (slow) Stopband Rejection..................................................................... 83

Figure 51. Single Speed (slow) Transition Band........................................................................... 83

Figure 52. Single Speed (slow) Transition Band (detail)............................................................... 84

Figure 53. Single Speed (slow) Passband Ripple......................................................................... 84

Figure 54. Double Speed (fast) Stopband Rejection..................................................................... 84

Figure 55. Double Speed (fast) Transition Band........................................................................... 84

Figure 56. Double Speed (fast) Transition Band (detail)............................................................... 84

Figure 57. Double Speed (fast) Passband Ripple......................................................................... 84

Figure 58. Double Speed (slow) Stopband Rejection................................................................... 85

Figure 59. Double Speed (slow) Transition Band ......................................................................... 85

Figure 60. Double Speed (slow) Transition Band (detail) ............................................................. 85

Figure 61. Double Speed (slow) Passband Ripple ....................................................................... 85

Figure 62. Quad Speed (fast) Stopband Rejection....................................................................... 85

Figure 63. Quad Speed (fast) Transition Band ............................................................................. 85

Figure 64. Quad Speed (fast) Transition Band (detail) ................................................................. 86

Figure 65. Quad Speed (fast) Passband Ripple ........................................................................... 86

Figure 66. Quad Speed (slow) Stopband Rejection...................................................................... 86

Figure 67. Quad Speed (slow) Transition Band............................................................................ 86

Figure 68. Quad Speed (slow) Transition Band (detail)................................................................ 86

Figure 69. Quad Speed (slow) Passband Ripple.......................................................................... 86

LIST OF TABLES

Table 1. Common OMCK Clock Frequencies............................................................................... 25

Table 2. Common PLL Output Clock Frequencies....................................................................... 25

Table 3. Slave Mode Clock Ratios................................................................................................26

Table 4. Serial Audio Port Channel Allocations ............................................................................ 26

Table 5. DAC De-Emphasis.......................................................................................................... 47

Table 6. Receiver De-Emphasis ...................................................................................................48

Table 7. Digital Interface Formats................................................................................................. 48

Table 8. ADC One-Line Mode....................................................................................................... 49

Table 9. DAC One-Line Mode....................................................................................................... 49

Table 10. RMCK Divider Settings .................................................................................................51

Table 11. OMCK Frequency Settings ........................................................................................... 52

Table 12. Master Clock Source Select.......................................................................................... 52

Table 13. AES Format Detection ..................................................................................................53

Table 14. Receiver Clock Frequency Detection............................................................................ 54

Table 15. Example Digital Volume Settings.................................................................................. 57

Table 16. ATAPI Decode .............................................................................................................. 59

Table 17. Example ADC Input Gain Settings................................................................................ 60

Table 18. TXP Output Selection.................................................................................................... 61

Table 19. Receiver Input Selection............................................................................................... 62

Table 20. Auxiliary Data Width Selection...................................................................................... 65

Table 21. PLL External Component Values.................................................................................. 78

Table 22. Revision History ........................................................................................................... 87

CS42518

1 CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics andspecifications are guaranteed over the Specified Operating Conditions. Typical per-

formance characteristics and specifications are derived from measurements taken at nominal supply voltages and

TA= 25° C.)

SPECIFIED OPERATING CONDITIONS

(AGND=DGND=0, all voltages with respect to ground;

OMCK=12.288 MHz; Master Mode)

ABSOLUTE MAXIMUM RATINGS

(AGND = DGND = 0 V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

Notes: 1. Anypinexcept supplies.Transientcurrents ofup to ±100mA on theanaloginput pins willnotcause SCR

latch-up.

2. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface

VA / VARX

VLS

VLC

4.75

3.13

1.8

5.0

3.3

5.0

5.25

Ambient Operating Temperature (power applied) CS42518-CQ

CS42518-DQ TA-10

-40 -

-+70

+85 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface

VA / VARX

VLS

VLC

-0.3

6.0

Input Current (Note 1) Iin -±10mA

Analog Input Voltage (Note 2) VIN AGND-0.7 VA+0.7 V

Digital Input Voltage Serial Port Interface

(Note 2) Control Port Interface

S/PDIF interface

VIND-S

VIND-C

VIND-SP

-0.3

VLS+ 0.4

VLC+ 0.4

VARX+0.4

Ambient Operating Temperature(power applied)CS42518-CQ

CS42518-DQ TA

-20

-50 +85

+95 °C

°C

Storage Temperature Tstg -65 +150 °C

CS42518

ANALOG INPUT CHARACTERISTICS

(TA= 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" =

DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise

specified. Full scale input sine wave, 997 Hz.; OMCK = 12.288 MHz; Single speed Mode CX_SCLK = 3.072 MHz;

Double Speed Mode CX_SCLK = 6.144 MHz; Quad Speed Mode CX_SCLK = 12.288 MHz.)

Parameter Symbol CS42518-CQ

Min Typ Max CS42518-DQ

Min Typ Max Unit

Single Speed Mode (Fs=48 kHz)

Dynamic Range A-weighted

unweighted 108

105 114

111 -

-106

103 114

111 -

-dB

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB

THD+N -

-100

-91

-51

-94

-100

-91

-51

-92

Double Speed Mode (Fs=96 kHz)

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

106

103

114

111

108

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-94

-100

-91

-51

-97

-92

Quad Speed Mode (Fs=192 kHz)

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

108

105

114

111

108

106

103

114

111

108

Total Harmonic Distortion + Noise

(Note 3) -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N -

-100

-91

-51

-97

-94

-100

-91

-51

-97

-92

Dynamic Performance for All Modes

Interchannel Isolation - 110 - - 110 - dB

Interchannel Phase Deviation - 0.0001 - - 0.0001 - Degree

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - +/-100 --+/-100-ppm/°C

Offset Error HPF_FREEZE enabled

HPF_FREEZE disabled -

-0

100 -

-0

100 -

-LSB

LSB

Analog Input

Full-scale Differential Input Voltage 1.05VA 1.10VA 1.16VA 0.99VA 1.10VA 1.21VA Vpp

Input Impedance(differential) (Note

4) 37 - - 37 - - k

Ω

Common Mode Rejection Ratio CMRR - 82 - - 82 - dB

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current

2.7

0.01

2.7

0.01

Ω

CS42518

Notes: 3. Referred to the typical full-scale voltage.

4. Measured between AIN+ and AIN-

A/D DIGITAL FILTER CHARACTERISTICS

Notes: 5. The filter frequency response scales precisely with Fs.

6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

FILT+ Nominal Voltage

Output Impedance

Maximum allowable DC current

5.0

0.01

5.0

0.01

Ω

Parameter Symbol Min Typ Max Unit

Single Speed Mode (2 to 50 kHz sample rates)

Passband (-0.1 dB) (Note 5) 0 - 0.47 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 5) 0.58 - - Fs

Stopband Attenuation -95 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs- s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

Double Speed Mode (50 to 100 kHz sample rates)

Passband (-0.1 dB) (Note 5) 0 - 0.45 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 5) 0.68 - - Fs

Stopband Attenuation -92 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs- s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

Quad Speed Mode (100 to 192 kHz sample rates)

Passband (-0.1 dB) (Note 5) 0 - 0.24 Fs

Passband Ripple - - ±0.035 dB

Stopband (Note 5) 0.78 - - Fs

Stopband Attenuation -97 - - dB

Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs- s

Group Delay Variation vs. Frequency ∆tgd --0.0µs

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB (Note 6) -1

20 -

-Hz

Phase Deviation @ 20 Hz (Note 6) - 10 - Deg

Passband Ripple - - 0 dB

Filter Setting Time - 105/Fs - s

CS42518

ANALOG OUTPUT CHARACTERISTICS

(TA= 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" =

DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise

specified.; Full scale output 997 Hz sine wave, Test load RL= 3 kΩ, CL= 30 pF; OMCK = 12.288 MHz; Single

speed Mode, CX_SCLK = 3.072 MHz; Double Speed Mode, CX_SCLK = 6.144 MHz; Quad Speed Mode,

CX_SCLK = 12.288 MHz.)

Notes: 7. One-half LSB of triangular PDF dither is added to data.

8. Performance limited by 16-bit quantization noise.

Parameter Symbol CS42518-CQ

Min Typ Max CS42518-DQ

Min Typ Max Unit

Dynamic performance for all modes

Dynamic Range(Note 7)

24-bit A-Weighted

unweighted

16-bit A-Weighted

(Note 8) unweighted

104

101

110

107

102

110

107

Total Harmonic Distortion + Noise

24-bit 0 dB

-20 dB

-60 dB

16-bit 0 dB

(Note 8) -20 dB

-60 dB

THD+N -

-100

-91

-51

-94

-74

-34

-94

-100

-91

-51

-94

-74

-34

-92

Idle Channel Noise/Signal-to-noise

ratio (A-Weighted) -110 - -110 -dB

Interchannel Isolation (1 kHz) - 90 - - 90 - dB

Analog Output Characteristics for all modes

Full Scale Differential Output .89VA .94VA .99VA .84VA .94VA 1.04VA Vpp

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - 100 - - 100 - ppm/°C

Output Impedance ZOUT -100 - -100 - Ω

AC-Load Resistance RL3- -3- -kΩ

Load Capacitance CL- - 30 - - 30 pF

CS42518

D/A DIGITAL FILTER CHARACTERISTICS

Notes: 9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 46 to 69) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

10. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.

Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single Speed Mode.

Parameter Fast Roll-Off Slow Roll-Off UnitMin Typ Max Min Typ Max

Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-0.4535

0.4998 0

-0.4166

0.4998 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB

StopBand 0.5465 - - 0.5834 - - Fs

StopBand Attenuation (Note 10) 90 - - 64 - - dB

Group Delay - 12/Fs - - 6.5/Fs - s

Passband Group Delay Deviation 0 - 20 kHz - - ±0.41/Fs - ±0.14/Fs s

De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

±0.23

±0.14

±0.09

±0.23

±0.14

±0.09

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-0.4166

0.4998 0

-0.2083

0.4998 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB

StopBand 0.5834 - - 0.7917 - - Fs

StopBand Attenuation (Note 10) 80 - - 70 - - dB

Group Delay - 4.6/Fs - - 3.9/Fs - s

Passband Group Delay Deviation 0 - 20 kHz - - ±0.03/Fs - ±0.01/Fs s

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-0.1046

0.4897 0

-0.1042

0.4813 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB

StopBand 0.6355 - - 0.8683 - - Fs

StopBand Attenuation (Note 10) 90 - - 75 - - dB

Group Delay - 4.7/Fs - - 4.2/Fs - s

Passband Group Delay Deviation 0 - 20 kHz - - ±0.01/Fs - ±0.01/Fs s

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