ComBlock COM-1826 Manuale utente
COM-1826 TDRSS SPREAD-
SPECTRUM MODEM
Key Features
TDRSS spread-spectrum modem comprising
oDemodulator with two input types:
GbE LAN SDDS-formatted input
stream or RF input.
oModulator with baseband or RF output.
BPSK and SQPN spread-spectrum modulation
Convolutional Viterbi error correction: K=7
Rate ½
Programmable 1023- (forward command link)
or 2047-chip (return mode 2 link) periodic I and
Q Gold codes
Programmable bit rates from 1 to 150 Kbits s
on each channel. Two independent bit
synchronizers to acquire and track each channel
bit stream.
120-bin parallel code search for fast code
acquisition. False code lock prevention.
Built-in Bit Error Rate measurement for PRBS-
11 test sequences.
Demodulation performances: within 1.5 dB
from theory at threshold Eb No of 2 dB.
Demodulated bits encapsulated in UDP frames
and sent out to the LAN. Support for IGMPv2
multicast addressing.
Monitoring:
oReceiver lock, Carrier frequency error,
SNR
ComScope –enabled: key internal signals
can be captured in real-time and displayed on
host computer.
90VAC – 264VAC power supply
Options:
o1-3 receivers per 1 RU chassis
oModulator with RF output
oDemodulator RF input
For the latest data sheet, please refer to the ComBlock
web site: http: www.comblock.com download com1826.pdf.
These specifications are subject to change without notice.
For an up-to-date list of ComBlock modules, please
refer to http: www.comblock.com product_list.html .
MSS • 845-N Quince Orchard Boulevard • Gaithersburg, Maryland 20878 • U.S.A.
Telephone: (240) 631-1111 Facsimile: (240) 631-1676 www.ComBlock.com
© MSS 2016 Issued 11 27 2016
Block Diagram
Carrier
tracking
loop (PLL+AFC)
Carrier
NCO
Code
timing
NCO
PSK symbol
decoding
Demod lated
data bits
LPF
Monitoring
Freq ency error
Code lock Monitoring
Info
Code
replica
generation
Despreading
Coherent I&D
Non-coherent I&D
Re-sampling
Digital
freq ency
translation
Noise power
x NACQ
parallel
detection
circ its
Code
tracking
loop
Skip
1/2 chips
False
code lock
detection
Code
acq isition
State
machine
Carrier lock
early
center
late
bins
3baseband
complex
samples
Despreading
with on-time
code replica to PSK
demod lator
I&D
Symbol
timing
NCO
to PSK
demod lator
Symbol
timing
loop
PSK
demodulator
DSSS
demodulator
3-channel receiver
Configuration
This ComBlock assembly comprising several ComBlock modules can be monitored and controlled centrally
over a single connection with a host computer. Connection types include built-in types:
USB
TCP-IP LAN
The module configuration is stored in non-volatile memory.
Configuration Basic)
The easiest way to configure the COM-1826 is to use the ComBlock Control Center software supplied with
the module on CD. In the ComBlock Control Center window detect the ComBlock module(s) by clicking the
Detect button, next click to highlight the COM-1826 module to be configured, next click the Settings
button to display the Settings window shown below.
3
4
5
Configuration Advanced)
Alternatively, users can access the full set of configuration features by specifying 8-bit control registers as
listed below. These control registers can be set manually through the ComBlock Control Center or by software
using the ComBlock API (see www.comblock.com download M&C_reference.pdf)
All control registers are read write. Definitions for the Control registers and Status registers are provided below.
6
Control Registers
The module configuration parameters are stored in
volatile (SRT command) or non-volatile memory
(SRG command). All control registers are
read write.
Several key parameters are computed on the basis
of the 125 MHz internal processing clock fclk_p:
frequency translation, chip rate, etc.
Built-in DSSS demodulator
Parameters Configuration
SDDS-
formatted
stream input
selection
1 = UDP port 29495
0 = TCP port 1028
REG0(0)
Demod input
selection
0 = SDDS LAN
2 = A D converters baseband
3 = A D converters IF undersampling
4 = internal modulator loopback
REG28(7:5)
I Code Linear feedback shift register initialization.
As per [1]
REG1 LSB
REG2(2:0) MSb
Q Code REG3 LSB
REG4(2:0) MSb
Code mode 0 = forward command link
1 = return mode 2 link
See SNIP for details
REG27(4)
reserved REG27(7:5) = “000”
CIC_R Decimation ratio.
Largest integer less than
input sampling rate 4*chip rate
REG2(7:3): lsbs
REG4(7:3): msbs
Chip rate
(fchip rate)
The nominal chip rate is 3.077799479166
Mchips s. However, the design is somewhat
more flexible. Alternative chip rates can be
entered here
32-bit integer expressed as
fchip rate * 232 fclk_p.
The maximum practical chip rate is fclk_p 2.
Nominal chip rate: 0x064DA741
The maximum allowed error between
transmitted and received chip rate is + -
100ppm.
REG5 (LSB) – REG8 (MSB)
I channel symbol
rate
fsymbol_rate
The I-channel symbol rate can be set
independently of the spreading code period
as
fsymbol_rate * 232 fclk_p
Example: “00346DC6” represents 100
Ksymbols s.
REG9 (LSB) – REG12 (MSB)
Q channel
symbol rate
fsymbol_rate
The Q-channel symbol rate can be set
independently of the spreading code period
as
fsymbol_rate * 232 fclk_p
REG13 (LSB) – REG16 (MSB)
I channel
spreading
factor
(Processing
gain)
Approximate (i.e rounded) ratio of chip
rate symbol rate
REG17 (LSB)
REG18(4:0) MSb
Q channel
spreading
factor
(Processing
gain)
Approximate (i.e rounded) ratio of chip
rate symbol rate
REG19 (LSB)
REG20(4:0) MSb
Nominal input
center
frequency (fc)
The nominal center frequency is a fixed
frequency offset applied to the SDDS input
samples. It is used for fine frequency
corrections, for example to correct clock
drifts.
32-bit signed integer (2’s complement
representation) expressed as
fc * 232 fclk_p
In addition to this fixed value, an optional
time-dependent frequency profile can be
entered. See frequency profile table.
REG21 (LSB) – REG24 (MSB)
Reserved REG25
Spectrum
inversion
Invert Q bit
0 = off
1 = on
REG26(0)
BPSK SQPN 0 = BPSK
1 = SQPN
REG26(1)
SQPN
single double
source
0 = different data on I and Q channels
(including the case when bits of a single
input bit stream are sent alternatively to the
I Q channels). Independent symbol rates on
I Q channels. Uses two FEC decoders.
1 = identical data on I and Q channels (prior
to coherent sum). Uses one FEC decoder.
7
REG26(2)
Alternating I Q
bits
Alternating bits are sent on the I and Q
channels. The symbol rate must be identical
on both I and Q channels. Two independent
FEC decoders are used on the I and Q paths
respectively.
Enabled(1) Disabled(0)
REG26(7)
½ symbol delay
on the Q path
The Q bits received with a ½ symbol delay
with respect to the I bits.
Enabled(1) Disabled(0)
REG26(6)
Encoding 0 = NRZ-L
1 = NRZ-M
2 = NRZ-S
4 = Biphase-L
REG26(5:3)
AGC response
time
Users can to optimize AGC response time
while avoiding instabilities (depends on
external factors such as gain signal filtering
at the RF front-end and chip rate). The
AGC_DAC gain control signal is updated as
follows
0 = every chip,
1 = every 2 input chips,
2 = every 4 input chips,
3 = every 8 input chips, etc….
10 = every 1000 input chips.
Valid range 0 to 14.
REG28(4:0)
Viterbi decoding Disable (0) Enable (1)
REG27(1)
Viterbi decoder
G2 parity bit
inversion
No (0) Yes (1)
REG27(2)
Select BER
tester input 0 = I,
1 = Q
REG27(3)
Built-in DSSS modulator (when instantiated)
Parameters Configuration
DSSS modulator
enable
0 = disabled
1 = enabled
REG61(7)
Channel 1
modulator input
selection
0 = disabled
1 = TCP server at port 1280
2 = PRBS11 test sequence
3 = zeros
REG63(5:4)
Channel 2
modulator input
selection
0 = disabled
1 = TCP server at port 1281
2 = PRBS11 test sequence
3 = zeros
REG65(5:4)
I Code Linear feedback shift register
initialization.
As per [1]
REG62 LSB
REG63(2:0) MSb
Q Code REG64 LSB
REG65(2:0) MSb
Code mode 0 = forward command link (see SNIP)
1 = return mode 2 link
See SNIP for details
REG65(3)
Chip rate
(fchip rate)
The nominal chip rate is 3.077799479166
Mchips s. However, the design is
somewhat more flexible. Alternative chip
rates can be entered here
32-bit integer expressed as
fchip rate * 232 fclk_p.
The maximum practical chip rate is fclk_p
2.
Nominal chip rate: 0x064DA730
REG66 (LSB) – REG69 (MSB)
I channel
symbol rate
fsymbol_rate
The I-channel symbol rate can be set
independently of the spreading code
period as
fsymbol_rate * 232 fclk_p
Example: 0x0346DC5 represents 100
Ksymbols s.
REG70 (LSB) – REG73 (MSB)
Q channel symbol
rate
fsymbol_rate
The Q-channel symbol rate can be set
independently of the spreading code
period as
fsymbol_rate * 232 fclk_p
REG74(LSB) – REG77 (MSB)
8
Modulated signal
amplitude
16-bit amplitude scaling factor for the
modulated signal.
The maximum level should be adjusted to
prevent saturation. Saturation can easily be
checked by visualizing the input signal
using ComScope.
REG29 = LSB
REG30 = MSB
Output center
frequency (fc)
Fixed frequency offset applied to the
output samples.
32-bit signed integer (2’s complement
representation) expressed as
fc * 232 fclk_p
REG81 (LSB) – REG78 (MSB)
Spectrum
inversion
Invert Q bit
0 = off
1 = on
REG61(0)
BPSK SQPN 0 = BPSK
1 = SQPN
REG61(1)
SQPN
single double
source
0 = different data on I and Q channels
(including the case when bits of a single
input bit stream are sent alternatively to the
I Q channels). Independent symbol rates on
I Q channels. Uses two FEC encoders.
1 = identical data on I and Q channels.
Uses one FEC encoder
REG61(2)
Alternating I Q
bits
When enabled, the input data stream is
demultiplexed into the I and Q paths. The
symbol rate must be identical on both I and
Q channels. Two independent FEC
encoders are used on the I and Q paths
respectively.
Enabled(1) Disabled(0)
REG60(7)
½ symbol delay
on the Q path
A ½ symbol delay can be added to the Q
modulator path
Enabled(1) Disabled(0)
REG60(6)
Data format
converter
Data format conversion from the NRZ-L
input to NRZ-L M S format prior to the
FEC encoder.
0 = NRZ-L to NRZ-L
1 = NRZ-L to NRZ-M
2 = NRZ-L to NRZ-S
REG61(5:3)
Convolutional
FEC encoding Disable (0) Enable (1)
REG61(6)
Additive White
Gaussian Noise
gain
16-bit amplitude scaling factor for additive
white Gaussian noise.
Because of the potential for saturation,
please check for saturation when changing
this parameter. Saturation can easily be
checked by visualizing the input signal
using ComScope.
REG31 = LSB
REG32 = MSB
External
transmitter gain
control
When using an external transceiver such as
the COM-350x family, the transmitter gain
can be controlled through the
TX_GAIN_CNTRL1 analog output signal.
Range 0 – 3.3V.
REG59: LSB, REG60(3:0): MSb
TX_ENB
control
The TX_ENB signal at the interface
controls the RF transmit circuit.
0 = off
1 = on
REG60(4)
etwork Interface
Parameters Configuration
MAC addresses LSB In order to ensure the uniqueness of
MAC addresses, users can define bits
7:1 through REG236(7:1).
The MAC addresses upper bits are
automatically tied to the nearly unique
FPGA DNA_ID. MAC address bit 0 is
either 0 (LAN1) or 1 (LAN2).
REG236(7:1).
IP1 multicast address
(LAN xB connector
on backpanel)
4-byte IPv4 address used for SDDS
input stream.
Example : 0x E1 00 00 01 designates
address 225.0.0.1
Use 0.0.0.0 to signify that multicasting
is not supported.
REG33 (MSB) – REG36 (LSB)
IP1 static address
(LAN xB connector
on backpanel)
4-byte IPv4 address used for SDDS
input stream.
Example : 0x AC 10 01 80 designates
address 172.16.1.128
The new address becomes effective
immediately (no need to reset the
ComBlock).
REG37 (MSB) - REG40 (LSB)
IP2 address (LAN xA
connector on
backpanel)
4-byte IPv4 address used for receiver
output, modulator inputs and
monitoring and control.
Example : 0x AC 10 01 80 designates
address 172.16.1.128
The new address becomes effective
immediately (no need to reset the
ComBlock).
REG41 (MSB) - REG44 (LSB)
Destination IP
address
4-byte IPv4 address
Destination IP address for UDP frames
9
with decoded data.
Example : 0x AC 10 01 80 designates
address 172.16.1.128
The new address becomes effective
immediately (no need to reset the
ComBlock).
REG45 (MSB) – REG48(LSB)
Destination ports I-channel data is routed to this user-defined
port number:
REG49(LSB) – REG50(MSB)
Q-channel data is routed to the incremented
port number.
Subnet mask REG51 (MSB) – REG54(LSB)
Gateway IP address REG55 (MSB) – REG58(LSB)
(Re-)Writing to the last control register REG81 is
recommended after a configuration change to enact the
change.
Status Registers
Parameters Monitoring
Hardware self-
check
At power-up, the hardware platform
performs a quick self check. The result is
stored in status registers SREG0-9
Properly operating hardware will result in
the following sequence being displayed:
SREG0-SREG9 = 01 F1 1D xx 1F 93 10
22 22 03
TCXO reference
clock presence
1 = detected
0 = missing
SREG9(0)
125 MHz internal
clock PLL lock
Indirectly confirms the presence of the
frequency reference (TCXO for firmware
option –A, external 10 MHz for firmware
option –B)
1 = locked
0 = unlocked
SREG9(1)
Input sampling rate The sampling rate, as read from the SDDS
input stream.
Format:
sampling_rate fclk *2^32
SREG10 = bit 7-0 (LSB)
SREG11 = bit 15 – 8
SREG12 = bit 23 – 16
SREG13(3:0) = bit 27 – 24 (MSB)
Time tag Last valid timetag read from the SDDS
input header. Expressed in 250ps units.
SREG14 (LSB) – SREG21(MSB)
Input frame counter Cumulative SDDS frame counter. Each
frame contains 1024 bytes = 256 complex
samples.
SREG22 (LSB) – SREG25(MSB)
Missing input frame
counter
Cumulative number of missing SDDS
frames. Should be zero.
SREG26 (LSB) – SREG27(MSB)
LAN1 MAC bad
CRC counter SREG28 (LSB) – SREG29(MSB)
MAC address Unique 48-bit hardware address (802.3). In
the form SREG30:SREG31:SREG32:
…:SREG35
Demodulator
carrier lock status
SREG36(0)
0 = unlocked or no input
1 = locked
Code lock status SREG36(1)
0 = unlocked or no input
1 = locked (1 s hysteresis)
Viterbi decoder1
synchronized
SREG36(2)
0 = not synchronized or no input
1 = synchronized
Viterbi decoder2 SREG36(3)
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