Cypress Semiconductor CY7C1006D Manuale utente
1-Mbit (256K x 4) Static RAM
CY7C106D
CY7C1006D
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05459 Rev. *E Revised February 22, 2007
Features
• Pin- and function-compatible with CY7C106B/CY7C1006B
• High speed
—t
AA =10 ns
• Low active power
—I
CC = 80 mA @ 10 ns
• Low CMOS standby power
—I
SB2 = 3.0 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• CY7C106D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1006D available in Pb-free 28-pin
300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected. The four input and output pins (IO0
through IO3) are placed in a high-impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the four IO pins (IO0
through IO3) is then written into the location specified on the
address pins (A0through A17).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the four IO pins.
Logic Block Diagram
IO0
IO1
IO2
IO3
SENSE AMPS
POWER
DOWN
CE
WE
OE
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
256K x 4
ARRAY
INPUT BUFFER
A0
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *E Page 2 of 11
Pin Configuration [2]
Selection Guide
CY7C106D-10
CY7C1006D-10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum Standby Current 3 mA
1
2
3
4
5
6
7
8
9
11
14 15
16
20
19
18
17
21
24
23
22
12
13
25
28
27
26
A
7
A
0
A
1
A
2
A
3
A
4
A
15
A
6
A
8
A
9
A
10
A
11
A
12
A
14
NC
OE
A
5
WE
IO
0
IO
1
IO
2
IO
3
V
CC
GND
10
Top View
SOJ
CE
A
13
A
16
A
17
Note
2. NC pins are not connected on the die.
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CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *E Page 3 of 11
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND [3] ... –0.5V to +6.0V
DC Voltage Applied to Outputs
in High-Z State [3] ...................................–0.5V to VCC + 0.5V
DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40°C to +85°C 5V ±0.5V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
7C106D-10
7C1006D-10 Unit
Min Max
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage [3] –0.5 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 µA
IOZ Output Leakage Current GND < VI <VCC, Output Disabled –1 +1 µA
ICC VCC Operating Supply Current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz 80 mA
83 MHz 72 mA
66 MHz 58 mA
40 MHz 37 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fmax
10 mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs
Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V, f=0
3mA
Note
3. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
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CY7C1006D
Document #: 38-05459 Rev. *E Page 4 of 11
Capacitance [4]
Parameter Description Test Conditions Max Unit
CIN: Addresses Input Capacitance TA= 25°C, f = 1 MHz, VCC = 5.0V 7 pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Thermal Resistance [4]
Parameter Description Test Conditions 300-Mil
Wide SOJ
400-Mil
Wide SOJ Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.16 58.76 °C/W
ΘJC Thermal Resistance
(Junction to Case)
40.84 40.54 °C/W
AC Test Loads and Waveforms [5]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns
30 pF*
OUTPUT
Z = 50
Ω
50 Ω
1.5V
(b)
(a)
5V
OUTPUT
5 pF
(c)
R1 480Ω
R2
255Ω
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
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CY7C1006D
Document #: 38-05459 Rev. *E Page 5 of 11
Switching Characteristics (Over the Operating Range) [6]
Parameter Description
7C106D-10
7C1006D-10 Unit
Min Max
Read Cycle
tpower [7] VCC(typical) to the first access 100 µs
tRC Read Cycle Time 10 ns
tAA Address to Data Valid 10 ns
tOHA Data Hold from Address Change 3 ns
tACE CE LOW to Data Valid 10 ns
tDOE OE LOW to Data Valid 5 ns
tLZOE OE LOW to Low Z 0 ns
tHZOE OE HIGH to High Z [8, 9] 5ns
tLZCE CE LOW to Low Z [9] 3ns
tHZCE CE HIGH to High Z [8, 9] 5ns
tPU [10] CE LOW to Power-Up 0 ns
tPD [10] CE HIGH to Power-Down 10 ns
Write Cycle [11, 12]
tWC Write Cycle Time 10 ns
tSCE CE LOW to Write End 7 ns
tAW Address Set-Up to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 7 ns
tSD Data Set-Up to Write End 6 ns
tHD Data Hold from Write End 0 ns
tLZWE WE HIGH to Low Z [9] 3ns
tHZWE WE LOW to High Z [8, 9] 5ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs
enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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CY7C1006D
Document #: 38-05459 Rev. *E Page 6 of 11
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
3mA
tCDR [4] Chip Deselect to Data Retention Time 0 ns
tR [13, 14] Operation Recovery Time tRC ns
Data Retention Waveform
4.5V4.5V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
V
CC
Switching Waveforms
Read Cycle No.1 (Address Transition Controlled) [15, 16]
Read Cycle No. 2 (OE Controlled) [16, 17]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
Notes
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
14. tr <3 ns for all speeds.
15. Device is continuously selected, OE and CE = VIL.
16. WE is HIGH for read cycle.
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CY7C1006D
Document #: 38-05459 Rev. *E Page 7 of 11
Write Cycle No. 1 (CE Controlled) [18, 19]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA IO
WE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA IO
OE
Notes
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. Data IO is high impedance if OE = VIH.
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CY7C1006D
Document #: 38-05459 Rev. *E Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW) [12, 19]
Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C106D-10VXI 51-85032 28-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1006D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free)
Please contact your local Cypress sales representative for availability of these parts.
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA IO
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CY7C1006D
Document #: 38-05459 Rev. *E Page 9 of 11
Package Diagrams
Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031
MIN.
MAX.
PIN 1 ID
0.291
0.300
0.050
TYP.
0.007
0.013
0.330
0.350
0.120
0.140
0.025 MIN.
0.262
0.272
0.697
0.713
0.013
0.019 0.014
0.020
0.032
0.026
A
A
DETAIL
EXTERNAL LEAD DESIGN
OPTION 1 OPTION 2
114
15 28
0.004
SEATING PLANE
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
3. DIMENSIONS IN INCHES
51-85031-*C
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CY7C106D
CY7C1006D
Document #: 38-05459 Rev. *E Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
PIN 1 I.D
.435
.395 .445
.405
.128
.148
.360
.380
.026
.015
.032
.020
DIMENSIONS IN INCHES MIN.
MAX.
.025 MIN.
.007
.013
.720
.730
114
15 28
0.004
SEATING PLANE
51-85032-*B
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