Cypress Semiconductor NoBL CY7C1470BV33 Manuale utente

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined SRAM with NoBL™ Architecture

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-15031 Rev. *C Revised February 29, 2008

Features

■Pin-compatible and functionally equivalent to ZBT™

■Supports 250 MHz bus operations with zero wait states

❐Available speed grades are 250, 200, and 167 MHz

■Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■Fully registered (inputs and outputs) for pipelined operation

■Byte Write capability

■Single 3.3V power supply

■3.3V/2.5V IO power supply

■Fast clock-to-output time

❐3.0 ns (for 250-MHz device)

■Clock Enable (CEN) pin to suspend operation

■Synchronous self-timed writes

■CY7C1470BV33, CY7C1472BV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-ball FBGA package. CY7C1474BV33

available in Pb-free and non-Pb-free 209-ball FBGA package

■IEEE 1149.1 JTAG Boundary Scan compatible

■Burst capability—linear or interleaved burst order

■“ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back read

or write operations with no wait states. The CY7C1470BV33,

CY7C1472BV33, and CY7C1474BV33 are equipped with the

advanced (NoBL) logic required to enable consecutive read or

write operations with data beingtransferred on everyclock cycle.

This feature dramatically improves the throughput of data in

systems that require frequent read or write transitions. The

CY7C1470BV33, CY7C1472BV33, andCY7C1474BV33 arepin

compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

Write operations are controlled by the Byte Write Selects

(BWa–BWdfor CY7C1470BV33, BWa–BWb for

CY7C1472BV33, and BWa–BWhfor CY7C1474BV33) and a

Write Enable (WE) input. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 3.0 3.0 3.4 ns

Maximum Operating Current 500 500 450 mA

Maximum CMOS Standby Current 120 120 120 mA

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 2 of 30

Logic Block Diagram – CY7C1470BV33 (2M x 36)

Logic Block Diagram – CY7C1472BV33 (4M x 18)

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

WRITE

DRIVERS

SLEEP

CONTROL

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

WRITE

DRIVERS

ZZ Sleep

Control

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 3 of 30

Logic Block Diagram – CY7C1474BV33 (1M x 72)

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQ s

DQ P

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

CEN

WRITE

DRIVERS

Sleep

Control

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 4 of 30

Pin Configurations

DDQ

DQb

DDQ

DQb

DQa

DDQ

DQa

DDQ

DQc

DDQ

DQc

DQd

DDQ

DQd

DDQ

BWa

CLK

CEN

100

ADV/LD

CY7C1470BV33

DDQ

DQPa

DQa

DDQ

DQa

DDQ

DQa

DDQ

DQb

DDQ

DQb

DDQ

DQb

DQPb

DDQ

BWb

BWa

CLK

CEN

100

ADV/LD

MODE

CY7C1472BV33

BWd

MODE

BWc

DQc

DQPc

DQd

DQPb

DQb

DQa

DQPa

DQb

(2M x 36) (4M x 18)

BWb

DQc NC

NC(288)

NC(144)

NC(288)

NC(144)

DQPd

Figure 1. 100-Pin TQFP Pinout

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 5 of 30

Pin Configurations (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1470BV33 (2M x 36)

CY7C1472BV33 (4M x 18)

2345671

TDO

NC/576M

NC/1G

DQP

ACE

CEN

ACE2

MODE

DDQ

CLK WE

DDQ

TCKA0

TDI

NC V

NC/144M NC

DDQ

TMS

891011

NC/288M

ADV/LD

AANC

DDQ

NC DQP

DDQ

DQP

DDQ

2345671

TDO

NC/576M

NC/1G

DQPb

DQb

ACE1CE3

BWbCEN

ACE2

DQb

MODE

DQb

VDDQ

BWaCLK WE

VSS VSS VSS VSS

VDDQ VSS

VDD VSS VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD VSS

VDD VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCKA0

VSS TDI

DQbVSS

NC VSS

DQb

NC NC VSS VSS

VSS VSS

VSS

DQbNC

NC/144M NC

VDDQ

VSS

TMS

891011

NC/288M

ADV/LD A

OE AANC

VSS VDDQ NC DQPa

VDDQ

VDD NC DQa

DQa

VDD VDDQ

VDD VDDQ DQa

VDD NC

VDD NCVDD VDDQ DQa

VDDQ

VDD

VDD VDDQ

VDD VDDQ NC

VDDQ

VSS A

DQa

NC ZZ

DQaNC

DQa

VDDQ

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 6 of 30

Pin Configurations (continued)

CY7C1474BV33 (1M × 72)

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

123456789 1110

DQg

DQc

DQPg

DQh

DQd

DQPd

DQPc

DQc

DQh

DQPh

DQd

DQb

DQf

DQPf

DQa

DQe

DQPa

DQPb

DQf

DQa

DQPe

DQe

AAAA

NC NC

NC/144M A A NC/288M

AAA

AAAA1

AAA

NC/576M

NC NC

BWSbBWSf

BWSeBWSa

BWScBWSg

BWSd

BWSh

TMS TDI TDO TCK

NC MODE NC

CEN VSS

CLK NC VSS

VDD VDD VDD

VDD

VSS VSS

VSS

VSS VSS

VSS

NC/1G

VDD

CE3

CE1

CE2ADV/LD

VSS

VSS VSS VSS VSS

VDDQ

VSS

VSS NC VSS VSS

VSS VSS VSS VSS

VSS

VDDQ VDDQ VDDQ VDDQ

VDDQ NC VDDQ VDDQ

VDDQ VDDQ NC VDDQ VDDQ

VDDQ

VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 7 of 30

Table 1. Pin Definitions

Pin Name IO Type Pin Description

Input-

Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge

of the CLK.

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

Input-

Synchronous Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWacontrols DQa and DQPa, BWbcontrols DQb and DQPb,

BWccontrols DQcand DQPc, BWdcontrols DQd and DQPd, BWecontrols DQe and DQPe, BWf

controls DQf and DQPf, BWgcontrols DQg and DQPg, BWhcontrols DQh and DQPh.

WE Input-

Synchronous Write Enable Input, Active LOW.Sampledon the rising edge ofCLK if CEN isactive LOW.This

signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous Advance/Load Input Used to Advance the On-chip Address Counter or Load a New

Address.WhenHIGH (and CEN is assertedLOW)the internal burstcounteris advanced. When

LOW,anewaddresscanbeloadedintothedeviceforanaccess.Afterbeingdeselected,ADV/LD

must be driven LOW to load a new address.

CLK Input-

Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE1Input-

Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE2and CE3to select or deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1and CE3to select or deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select or deselect the device.

OE Input-

Asynchronous Output Enable, Active LOW. Combined with the synchronous logic block inside the device to

control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs.

When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during

thedataportionofawrite sequence,duringthe firstclockwhenemergingfrom adeselected state

and when the device has been deselected.

CEN Input-

Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

DQSIO-

Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQa–DQdare placed in a tri-state condition. The outputs are automat-

ically tri-stated during the data portion of a write sequence, during the first clock when emerging

from a deselected state, and when the device is deselected, regardless of the state of OE.

DQPXIO-

Synchronous BidirectionalDataParityIOLines.Functionally,thesesignalsareidenticaltoDQX.Duringwrite

sequences, DQPais controlled by BWa, DQPbis controlled by BWb, DQPcis controlled by BWc,

and DQPdis controlled by BWd, DQPeis controlled by BWe, DQPfis controlled by BWf, DQPg

is controlled by BWg, DQPhis controlled by BWh.

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGHselects the interleaved burst order.

PulledLOWselectsthelinearburstorder.MODEmustnotchangestatesduringoperation.When

left floating MODE defaults HIGH, to an interleaved burst order.

TDO JTAG Serial

Output

Synchronous

Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.

TDI JTAGSerial Input

Synchronous Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 8 of 30

Functional Overview

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

are synchronous-pipelined Burst NoBL SRAMs designed specif-

ically to eliminate wait states during read or write transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

ClockEnable inputsignal (CEN).IfCENis HIGH,the clocksignal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. All data outputs

pass through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (tCO) is 3.0 ns

(250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is

active LOW and ADV/LD is asserted LOW, the address

presented to the device is latched. The access can either be a

read or write operation, depending on the status of the Write

Enable (WE). BW[x] can be used to conduct Byte Write opera-

tions.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device has been deselected to

load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the input signal WE is

deasserted HIGH, and (4) ADV/LD is asserted LOW. The

address presented to the address inputs is latched into the

Address Register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock the

requested data is allowed to propagate through the output

provided OE is active LOW. After the first clock of the read

access the output buffers are controlled by OE and the internal

control logic. OE must be driven LOW to drive out the requested

data. During the second clock, a subsequent operation (read,

write, or deselect) can be initiated. Deselecting the device is also

pipelined. Therefore, when the SRAM is deselected at clock rise

by one of the chip enable signals, its output tri-states following

the next clock rise.

Burst Read Accesses

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

have an on-chip burst counter that enables the user to supply a

single address and conduct up to four reads without reasserting

the address inputs. ADV/LD must be driven LOW to load a new

address into the SRAM, as described in the Single Read

Accesses section. The sequence of the burst counter is deter-

mined by the MODE input signal. A LOW input on MODE selects

a linear burst mode, a HIGH selects an interleaved burst

sequence. Both burst counters use A0 and A1 in the burst

sequence, and wraps around when incremented sufficiently. A

HIGH input on ADV/LD increments the internal burst counter

regardless of the state of chip enables inputs or WE. WE is

latched at the beginning of a burst cycle. Therefore, the type of

access (read or write) is maintained throughout the burst

sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the Address Register. The write signals are latched

into the Control Logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for

CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for

CY7C1474BV33). In addition, the address for the subsequent

TMS TestModeSelect

Synchronous This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.

TCK JTAG Clock Clock Input to the JTAG Circuitry.

VDD Power Supply Power Supply Inputs to the Core of the Device.

VDDQ IO Power Supply Power Supply for the IO Circuitry.

VSS Ground Ground for the Device. Should be connected to ground of the system.

NC – No Connects. This pin is not connected to the die.

NC(144M,

288M,

576M, 1G)

–These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and

1G densities.

ZZ Input-

Asynchronous ZZ“Sleep”Input.ThisactiveHIGHinputplacesthedeviceinanon-timecritical“sleep”condition

with data integrity preserved. During normal operation, this pin must be LOW or left floating.

ZZ pin has an internal pull-down.

Table 1. Pin Definitions (continued)

Pin Name IO Type Pin Description

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 9 of 30

access (read, write, or deselect) is latched into the Address

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for

CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for

CY7C1474BV33) (or a subset for byte write operations, see

“Partial Write Cycle Description” on page 11 for details) inputs is

latched into the device and the write is complete.

The data written during the Write operation is controlled by BW

(BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33, and

BWa,b,c,d,e,f,g,h for CY7C1474BV33) signals. The

CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

provides Byte Write capability that is described in “Partial Write

Cycle Description” on page 11. Asserting the Write Enable input

(WE) with the selected BW input selectively writes to only the

desired bytes. Bytes not selected during a Byte Write operation

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations. Byte Write

capability has been included to greatly simplify read, modify, or

write sequences, which can be reduced to simple Byte Write

operations.

Because the CY7C1470BV33, CY7C1472BV33, and

CY7C1474BV33 are common IO devices, data must not be

driven into the device while the outputs are active. The OE can

be deasserted HIGH before presenting data to the DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for

CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for

CY7C1474BV33) inputs. Doing so tri-states the output drivers.

As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for

CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and

DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) are

automatically tri-stated during the data portion of a write cycle,

regardless of the state of OE.

Burst Write Accesses

The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33

has an on-chip burst counter that enables the user to supply a

single address and conduct up to four write operations without

reasserting the address inputs. ADV/LD must be driven LOW to

load the initial address, as described in “Single Write Accesses”

on page 8. When ADV/LD is driven HIGH on the subsequent

clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs

are ignored and the burst counter is incremented. The correct

BW (BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472V33,

and BWa,b,c,d,e,f,g,h for CY7C1474BV33) inputs must be driven

in each cycle of the burst write to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pendingwhenentering the“sleep” modeare notconsideredvalid

nor is the completion of the operation guaranteed. The device

must be deselected before entering the “sleep” mode. CE1, CE2,

and CE3, must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Table 2. Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address Second

Address Third

Address Fourth

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Table 3. Linear Burst Address Table (MODE = GND)

First

Address Second

Address Third

Address Fourth

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ >VDD − 0.2V 120 mA

tZZS Device operation to ZZ ZZ > VDD −0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

CY7C1470BV33

CY7C1472BV33, CY7C1474BV33

Document #: 001-15031 Rev. *C Page 10 of 30

Table 4. Truth Table

The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.[1, 2, 3, 4, 5, 6, 7]

Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Tri-State

Continue

Deselect Cycle None X L H X X X L L-H Tri-State

Read Cycle

(Begin Burst) External L L L H X L L L-H Data Out (Q)

Read Cycle

(Continue Burst) Next X L H X X L L L-H Data Out (Q)

NOP/Dummy Read

(Begin Burst) External L L L H X H L L-H Tri-State

Dummy Read

(Continue Burst) Next XL H XXHLL-H Tri-State

Write Cycle

(Begin Burst) External L L L L L X L L-H Data In (D)

Write Cycle

(Continue Burst) Next X L H X L X L L-H Data In (D)

NOP/Write Abort

(Begin Burst) None L L L L H X L L-H Tri-State

Write Abort

(Continue Burst) Next X L H X H X L L-H Tri-State

Ignore Clock Edge

(Stall) Current X L X X X X H L-H -

Sleep Mode None X H X X X X X X Tri-State

Notes

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see “Partial Write Cycle Description” on page 11 for details.

2. Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page 11 for details.

3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQsand DQP[a:d] = tri-state when OE is

inactive or when the device is deselected, and DQs= data when OE is active.

[+] Feedback

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