Cypress Semiconductor CY7C1019CV33 Manuale utente

128K x 8 Static RAM

CY7C1019CV33

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05130 Rev. *F Revised August 3, 2006

Features

• Pin and function compatible with CY7C1019BV33

•Highspeed

—t

AA = 10 ns

• CMOS for optimum speed/power

• Data retention at 2.0V

• Center power/ground pinout

• Automatic power-down when deselected

• Easy memory expansion with CE and OE options

• Available in Pb-free and non Pb-free 48-ball VFBGA,

32-pin TSOP II and 400-mil SOJ package

Functional Description

The CY7C1019CV33 is a high-performance CMOS static

RAM organized as 131,072 words by 8 bits. Easy memory

expansion is provided by an active LOW Chip Enable (CE), an

active LOW Output Enable (OE), and tri-state drivers. This

device has an automatic power-down feature that significantly

reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O0through I/O7) is then written into the location

specified on the address pins (A0through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O0through I/O7) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

The CY7C1019CV33 is available in Standard 48-ball FBGA,

32-pin TSOP II and 400-mil-wide SOJ packages

Logic Block Diagram Pin Configuration

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUTBUFFER

POWER

DOWN

I/O0

I/O1

I/O2

I/O3

128K x 8

ARRAY

I/O7

I/O6

I/O5

I/O4

A11

A13

A12

A10

A16

14 19

Top View

SOJ/TSOP II

15 17

I/O0

I/O1

VCC

A13

A16

A15

I/O7

I/O6

A12

A11

A10

I/O2

I/O4

VCC

I/O5

I/O3

VSS

A14

VSS

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 2 of 10

Pin Configuration[1]

Selection Guide

-10 -12 -15 Unit

Maximum Access Time 10 12 15 ns

Maximum Operating Current 80 75 70 mA

Maximum Standby Current 5 5 5 mA

Note:

1. NC pins are not connected on the die.

VCC

A16

A1CE

I/O0

I/O1

I/O2

I/O3

VSS

A10

VSS

I/O7

A13

VCC

I/O6

I/O4I/O5

A11

A14

A12

A15

NC NC

48-ball VFBGA

(Top View)

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 3 of 10

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND[2] ....–0.5V to +4.6V

DC Voltage Applied to Outputs

in High-Z State[2]....................................–0.5V to VCC + 0.5V

DC Input Voltage[2].................................–0.5V to VCC + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-up Current......................................................>200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 3.3V ±10%

Industrial –40°C to +85°C3.3V ±10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

–10 –12 –15

UnitMin. Max. Min. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min.,

IOH = –4.0 mA 2.4 2.4 2.4 V

VOL Output LOW Voltage VCC = Min.,

IOL = 8.0 mA 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC+0.3 2.0 VCC + 0.3 V

VIL Input LOW Voltage[2] –0.3 0.8 –0.3 0.8 –0.3 0.8 V

IIX Input Leakage Current GND < VI< VCC –1 +1 –1 +1 –1 +1 µA

IOZ Output Leakage

Current GND < VI <VCC,

Output Disabled –1 +1 –1 +1 –1 +1 µA

ICC VCC Operating

Supply Current VCC = Max.,

IOUT = 0 mA,

f = fMAX = 1/tRC

80 75 70 mA

ISB1 Automatic CE

Power-down Current

—TTL Inputs

Max. VCC, CE > VIH

VIN > VIH or

VIN < VIL, f = fMAX

15 15 15 mA

ISB2 Automatic CE

Power-down Current

—CMOS Inputs

Max. VCC,

CE > VCC – 0.3V,

VIN > VCC – 0.3V,

or VIN < 0.3V, f = 0

555mA

Capacitance[3]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 5.0V 8pF

COUT Output Capacitance 8 pF

Notes:

2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.

3. Tested initially and after any design or process changes that may affect these parameters.

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 4 of 10

AC Test Loads and Waveforms[4]

Switching Characteristics Over the Operating Range[5]

Parameter Description

-10 -12 -15

UnitMin. Max. Min. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 10 12 15 ns

tAA Address to Data Valid 10 12 15 ns

tOHA Data Hold from Address Change 3 3 3ns

tACE CE LOW to Data Valid 10 12 15 ns

tDOE OE LOW to Data Valid 567ns

tLZOE OE LOW to Low Z 000ns

tHZOE OE HIGH to High Z[6, 7] 567ns

tLZCE CE LOW to Low Z[7] 333ns

tHZCE CE HIGH to High Z[6, 7] 567ns

tPU[8] CE LOW to Power-Up 000ns

tPD[8] CE HIGH to Power-Down 10 12 15 ns

Write Cycle[9, 10]

tWC Write Cycle Time 10 12 15 ns

tSCE CE LOW to Write End 8 9 10 ns

tAW Address Set-Up to Write End 8 9 10 ns

tHA Address Hold from Write End 0 0 0ns

tSA Address Set-Up to Write Start 0 0 0ns

tPWE WE Pulse Width 78

10 ns

tSD Data Set-Up to Write End 5 6 8ns

tHD Data Hold from Write End 0 0 0ns

tLZWE WE HIGH to Low Z[7] 333ns

tHZWE WE LOW to High Z[6, 7] 567ns

Notes:

4. AC characteristics(except High-Z) for all speeds are tested using the Thevenin load shown in Figure (a). High-Z characteristicsare tested for all speeds using

the test load shown in Figure (c).

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6. tHZOE, tHZCE,and tHZWE are specified with a load capacitance of 5pF as in part (d) of AC Test Loads. Transition is measured ±500 mVfrom steady-state voltage.

7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

8. This parameter is guaranteed by design and is not tested.

9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of

anyof thesesignalscanterminatethewrite. Theinputdataset-upandholdtiming shouldbe referencedtotheleadingedge ofthesignal thatterminatesthewrite.

10.The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

3.3V

OUTPUT

30 pF

(a)

R 317Ω

351Ω

Rise Time: 1 V/ns Fall Time: 1 V/ns

(b)

3.3V

OUTPUT

5 pF

(c)

R 317Ω

351Ω

High-Z characteristics:

[+] Feedback

CY7C1019CV33

Document #: 38-05130 Rev. *F Page 5 of 10

Switching Waveforms

Read Cycle No. 1[11, 12]

Read Cycle No. 2 (OE Controlled)[12, 13]

Write Cycle No. 1 (CE Controlled)[14, 15]

Notes:

11.Device is continuously selected. OE, CE = VIL.

12.WE is HIGH for read cycle.

13.Address valid prior to or coincident with CE transition LOW.

14.Data I/O is high impedance if OE = VIH.

15.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE tHZCE

tPD

HIGH

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

CURRENT

tWC

DATA VALID

tAW

tSA

tPWE

tHA

tHD

tSD

tSCE

ADDRESS

DATA I/O

[+] Feedback

CY7C1019CV33

Document #: 38-05130 Rev. *F Page 6 of 10

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]

Write Cycle No. 3 (WE Controlled, OE LOW)[15]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

DATAIN VALID

ADDRESS

DATA I/O

NOTE 16

DATA VALID

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

ADDRESS

DATA I/O NOTE 16

Truth Table

CE OE WE I/O0–I/O7Mode Power

H X X High Z Power-Down Standby (ISB)

L L H Data Out Read Active (ICC)

L X L Data In Write Active (ICC)

L H H High Z Selected, Outputs Disabled Active (ICC)

Note:

16.During this period the I/Os are in the output state and input signals should not be applied.

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 7 of 10

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

10 CY7C1019CV33-10VC 51-85033 32-pin 400-Mil Molded SOJ Commercial

CY7C1019CV33-10ZXC 51-85095 32-pin TSOP II (Pb-Free)

CY7C1019CV33-10ZXI 32-pin TSOP II (Pb-Free) Industrial

12 CY7C1019CV33-12VC 51-85033 32-pin 400-Mil Molded SOJ Commercial

CY7C1019CV33-12ZC 51-85095 32-pin TSOP II

CY7C1019CV33-12ZXC 32-pin TSOP II (Pb-Free)

CY7C1019CV33-12VI 51-85033 32-pin 400-Mil Molded SOJ Industrial

CY7C1019CV33-12BVXI 51-85150 48-ball VFBGA (Pb-Free)

15 CY7C1019CV33-15VC 51-85033 32-pin 400-Mil Molded SOJ Commercial

CY7C1019CV33-15VXC 51-85033 32-pin 400-Mil Molded SOJ (Pb-Free)

CY7C1019CV33-15ZXC 51-85095 32-pin TSOP II (Pb-Free)

CY7C1019CV33-15ZXI 51-85095 32-pin TSOP II (Pb-Free) Industrial

Package Diagrams

51-85033-*B

32-pin (400-Mil) Molded SOJ (51-85033)

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 8 of 10

Package Diagrams (continued)

51-85095-**

32-pin TSOP II (51-85095)

[+] Feedback

CY7C1019CV33

Document #: 38-05130 Rev. *F Page 9 of 10

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

48-ball VFBGA (6 x 8 x 1 mm) (51-85150)

51-85150-*D

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CY7C1019CV33

Document #: 38-05130 Rev. *F Page 10 of 10

Document History Page

Document Title: CY7C1019CV33 128K x 8 Static RAM

Document Number: 38-05130

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 109245 12/16/01 HGK New Data Sheet

*A 113431 04/10/02 NSL AC Test Loads split based on speed

*B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved ICC limits

*C 119796 10/11/02 DFP Updated standby current from 5 nA to 5 mA

*D 123030 12/17/02 DFP Updated Truth Table to reflect single Chip Enable option

*E 419983 See ECN NXR Added 48-ball VFBGA Package

Added lead-free parts in Ordering Information Table

Replaced Package Name column with Package Diagram in the Ordering

Information Table

*F 493543 See ECN NXR Removed 8 ns speed bin from Product offering

Added note #1 on page #2

Changed the description of IIX from Input Load Current to

Input Leakage Current in DC Electrical Characteristics table

Removed IOS parameter from DC Electrical Characteristics table

Updated Ordering Information

[+] Feedback

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