Cypress FR81S CY91F52 Series Istruzioni operative

 
www.cypress.com Document No. 002-09375 Rev. *B 1 
AN209375 
Recommendation for Hardware Setup 32-Bit FR81S Family 
 
 
This application note describes how to set up a hardware environment for Cypress FR81S MCUs. As an example, the 
CY91F52x MCU is used. 
Contents 
1Introduction..................................................................1 
2Minimal System...........................................................2 
2.1 Schematic...........................................................2 
2.2 Serial Interface....................................................2 
2.3 Power supply ......................................................2 
2.4 Analog Digital Converter Supply Pins.................2 
2.5 Analog Input Pins................................................3 
2.6 Reset Pin (RSTX) ...............................................4 
2.7 Non maskable Interrupt Pin (NMIX)....................4 
2.8 C-Pin...................................................................5 
2.9 Clock Source.......................................................5 
2.10 Mode Pins...........................................................6 
2.11 Not Connected Pins............................................6 
2.12 Debug Interface connection................................7 
3Layout and Electromagnetic Compatibility...................8 
3.1 General...............................................................8 
3.2 Power supply Pins ..............................................8 
3.3 Oscillator Pins.....................................................9 
3.4 Power Line Routing.............................................9 
3.5 Power Supply Decoupling.................................10 
3.6 Recommended Power Supply Circuit ...............12 
3.7 Reset circuit......................................................13 
3.8 Quartz Crystal Placement and Signal Routing..16 
3.9 Test points........................................................18 
3.10 Other documents ..............................................18 
4Port Input / Unused Pins / Latch-up...........................19 
4.1 Port Input / Unused Pins...................................19 
4.2 Latch-up consideration (switch) ........................20 
4.3 5 V Tolerant Input pins......................................24 
5Flash Programming Connection................................25 
5.1 Overview...........................................................25 
5.2 Serial programming via UART0........................25 
5.3 Serial programming via MDI interface...............27 
5.4 Parallel programming interface.........................29 
5.5 Security function ...............................................29 
6Reset Behavior of IO port pins ..................................30 
7Additional Information................................................30 
Worldwide Sales and Design Support.............................32 
Cypress Developer Community.......................................32 
Technical Support...........................................................32 
 
1 Introduction 
This design guide describes design restrictions and recommendations regarding signal wiring and the electrical power 
system of the MCU. For more details about the device features and its relevant settings, please refer to the FR81S 
Hardware Manual and its corresponding Datasheet for electrical characteristics. 
 

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 2

2 Minimal System

This chapter gives an example for a minimum hardware system.

2.1 Schematic

The following graphic shows a schematic of a minimum hardware system. Note that for other MCU families a different

pinning is needed.

Figure 1. Principal Schematic for Minimal Requirements

*1 only needed for dual clock devices.

*2 please refer to chapter 3.6 Recommended Power Supply Circuit.

2.2 Serial Interface

The “PC connection” section is only needed, if no 5 V external serial data lines for programming exist. The MAX232 is

a standard level shifter, which converts the 5 V levels of the MCU to ±12V RS232V24 levels and vice versa.

If you use a 3.3 V system a MAX3232 is recommended.

Please consider, that the internal charge pumps of the level shifter can produce noise on the +5 Volts line, which can

influence the ADC, if AVCCn and AVRHn are directly (unfiltered) connected to it.

2.3 Power supply

The power supply should be from 2.7 Volts to 5.5 Volts for normal usage. If a different supply voltage is used please

refer to the corresponding data sheet.

2.4 Analog Digital Converter Supply Pins

The analog converter supply pins (AVCCn, AVRHn / AVRLn, AVSSn) should be connected even if the ADC of the MCU

is not used. Please refer to our application note “mcu-an-300215-e-16fx_adc” for using the ADC and pin connection.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 3

2.5 Analog Input Pins

Because the ADC works with an internal sample capacitor (Cadc) you must be aware of the time needed to fully charge

this capacitor to the corresponding analog signal source voltage level by the end of the sample time.

When the external impedance is too high, the sampling period for analog voltages may not be sufficient. In this case, it

is recommended to connect an external capacitor (Cext, approx. 0.1 μF) to the analog input pin.

An input impedance maximum (Rext) 15k Ohm is recommended. So, an appropriate sample time has to be selected

depending on the impedance Rext and the capacitance Cext.

Please refer to Datasheet “A/D Converter” chapter for further information.

Figure 2. Analog Input Circuit Model

AN1 pin

Rext

Analog

Signal

Source #1 Cext

AN2 pin

Rext

Analog

Signal

Source #2 Cext

ANn pin

Rext

Analog

Signal

Source #n Cext

Cpad

Analog SW (Closed during sample)

Analog SW

Radc

Cadc

ADC

MCU

Table 1. Reference Values

Component

Value

AVcc

Cadc

8.30 pF (Max)

4.5 V… 5.5 V

Cadc

8.30 pF (Max)

3 V… 3.6 V

Radc

1.9K (Max)

4.5 V… 5.5 V

Radc

4.3K (Max)

3 V… 3.6 V

Cpin

5pF..15pF

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 4

2.6 Reset Pin (RSTX)

To reset the MCU a switch connects this pin to Vss (Ground). There is internal 50k pull-up resistor, but for high noise

requirements an external pull-up resistor with typical 10k is recommended. Additionally, a capacitor has to be connected

between Vss and the reset pin for debouncing the switch and for EMI protection. From experience a capacity of not

more than 1 nF is recommended. This capacity covers the most common frequency protection in a wide range. Higher

capacities and high impedance may cause latch-up effects together with an RSTX-Switch and low EMI protection. The

reset level of RSTX pins depends on the logical level on NMIX pin. Please refer to Hardware manual chapter 7 Reset.

Table 2. RSTX and NMIX Function

RSTX

NMIX

Function

Normal operation

Non maskable interrupt

External reset Reset (RST) Synchronous reset factor

Irregular reset Initialize reset (INIT) Asynchronous reset factor

(not guarantee that memory contents have not been destroyed by the reset)

2.7 Non maskable Interrupt Pin (NMIX)

The NMIX supports two several functions, (a) using as NMI input and (b) simultaneous assert of RSTX and NMIX pins

to generate an irregular reset. There is internal 50k pull-up resistor, but for high noise requirements an external pull-up

resistor with typical 10k is recommended.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 5

2.8 C-Pin

A 4.7 µF ceramic capacitor (dielectric X7R) must be connected very close to the C pin of the MCU. Furthermore, an

additional 100 nF (dielectric X7R) for higher noise frequencies is recommended. Otherwise the MCU may not operate

correct or will be damaged in worst case. Please refer to Datasheet chapter “Recommended operating conditions” for

further information.

Figure 3. Internal Voltage Regulator and C Pin

MCU GPIO GPIO GPIO

GPIOGPIOGPIOGPIO

GPIO GPIO GPIO

GPIOOSCGPIO

Vcc Vcc 5V

Vcc

Vss

GND

Vss

GND

Vss

GND

Vcc Vss

Internal 1.2V

Vss

GND

4.7µF

(ceramic X7R)

CORE

internal

voltage

regulator

*1 Note *1 : Vss pin

closest to C pin

2.9 Clock Source

A clock source must be provided to the MCU. Therefore, crystals or external clock signals can be used. For external

source pin X0 (X0A) is used whereby pin X1 (X1A) is not connected.

There are MCU derivatives for dual clock and single clock devices, the sub clock can be enabled by software. If sub

clock X0A pin is neither used as GPIO nor as clock input, the pin can be left open.

If you want to use only CR clock, then you need a MCU version with disabled CSV.

Please also refer to the chapter “Handling the device” in the corresponding hardware manual for details.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 6

2.10 Mode Pins

The mode pins set the current operation mode for the MCU. For a minimal system, only two modes are necessary:

Flash-Asynchronous-Serial-Programming-Mode and Run Mode.

In the case, you use the Serial Programming Mode the MD-pins need pull-up/pull-down resistors (typically 2k7

resistors). In order to increase the protection against ESD and EMI effects the PCB tracks should be as short as

possible.

If the Serial Programming Mode is not used the MD-pins can be connected directly to Vcc or GND. Please refer to

Datasheet chapter “Handling devices” for further information.

The following settings are used for the both modes mentioned above:

Table 3. Mode Pin Settings (x: does not care)

Mode

P006

MD0

MD1

Serial Programming Mode

Run (Internal Vector Mode)

2.11 Not Connected Pins

In default state after power-on reset usually the GPIO pins are in high-z state.

If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up.

Connect at least a 2k resistor to each unused pin in pull-up or pull-down configuration. Also, if I/O pins are not used,

they must be set to the output state for releasing or they must be set to the input state and treated in the same way as

for the input pins.

Concerning special use cases, it is referred to Port Input / Unused Pins / Latch-up for how to proceed with unused (not

connected) pins.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 7

2.12 Debug Interface connection

Debugging is only supported by the 50 Ohm single-wire debug system, which is shared with mode pin ‘DEBUGIF’.

Concerning current limitation by an external resistor on programming tool side and maximum clamping current/structure

at the ‘DEBUGIF’ pin specified values must be taken out of data sheet.

Figure 4. How to connect Debug System with Programming Connector

VCC

Debug

Connector R1

ECU

GND

DEBUGIF

MCU

L1L2

GND

(R1 = 43 R, R2 = 10 k, D1 e.g. HZM6.2Z4MFA-E, D2 schottky diode e.g. BAS40, Debug connector: SMA 50R connector

for development target boards.)

Table 4. SPEED-BOX General Specifications

Item

Specification

MDI bus maximum communication speed

(from MCU to SPEED-BOX)

50 Mbps

Does not depend on cable* length.

(* cable between SPEED-BOX and ECU)

MDI bus maximum communication speed

(from SPEED-BOX to MCU)

Cable* length 2 m or less : 25 Mbps

Cable* length 5 m or less : 12.5 Mbps

Cable* length 10 m or less : 6.25 Mbps

(* cable between SPEED-BOX and ECU)

L1 wiring length

As short as possible, keep less than 5 cm.

L2 wiring length

Less than 15 cm.

Please check for detailed OCDS layout design rules of the

MB2100-01-E (see chapter Flash Programming Connection)

and the chapter ‘On Chip Debugger: OCD’ of the hardware

manual.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 8

3 Layout and Electromagnetic Compatibility

This chapter gives some tips for layout design.

3.1 General

To avoid ESD problems and noise emission of the system some rules for the layout design have to be observed.

The most critical point is the C pin because this is the connection to the internal 1.2 V supply for the MCU core. Thus,

two decoupling capacitors have to be placed very near to this pin.

Also, the ground and Vcc routing has to be done carefully. Vcc lines should be routed in star shape. We recommend a

Vss ground plane on the mounting side just under the MCU. For both Vcc and Vss only one connection to the rest of

the circuit should be done, otherwise noise is carried-over from and to the MCU. This one connection should be used

for power supply filtering (PI-Filter with ferrite). Decoupling capacitors (DeCaps) have to be placed as near as possible

to the related pins. If they are placed too far away, their functionality becomes useless.

If possible all decoupling capacitors should be placed on the same mounting side as the MCU; otherwise the DeCaps

could be placed on bottom layer below the MCU.

PI-Filter prevents EMI from radiating from power supply planes. Keep maximum distance between IN and OUT

capacitor to avoid noise coupling at PI-Filter.

If crystals are used, they have to be placed as near as possible to the X1(A) pins, output of the inverter. The feedback

resistor of oscillator circuit (typ. 1Mohm) is already implemented internally. The evaluation of crystal/resonator and load

capacitor must be tested by the related crystal vendor by crystal matching test.

3.2 Power supply Pins

The following table shows the EMC critical pins and gives short information about how to connect them.

Table 5. Power Supply pins in use

Pin Name

Function

VCC

Dedicated power supply pins for IO buffer and crystal oscillator.

VCC5*

*Only for CY91570/590 series.

Dedicated power supply pins for IO buffer and crystal oscillator.

VCC3*

*Only for CY91590 series.

Power supply pins for 3V3 IO buffer.

VCCE*

*Only for CY91570 series.

Power supply pins for 3V3 IO buffer.

DVCC*, DVSS*

*Only for CY91570/590 series.

Power supply pins for high current output buffer pins.

VSS

Dedicated power supply (0 V) pins. (IO buffer, MCU core and crystal oscillator)

AVCCn

Dedicated power supply pins for the AD-converter (unit n).

AVRHn / AVRLn

Dedicated positive/negative reference voltage pin for the AD-converter (unit n).

AVSSn

Dedicated power supply pin (0 V) for the AD-converter (unit n).

Dedicated power supply pin for the internal power supply regulator (used to supply the

MCU core). External capacitor connected to this pin is required.

C_1*, C_2*, C_3*

*Only for CY91590 series.

Dedicated power supply pins for the internal power supply regulator (used to supply the

MCU core). External capacitors connected to these pins are required. Please refer to

datasheet “C Pin Connection Diagram” reference for further information.

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 9

3.3 Oscillator Pins

The following table shows the oscillator pins and gives short information about how to connect them.

Table 6. Oscillator pins in use

Pin Name

Function

X0, X0A

Oscillator input, if not used so shall be connected with pull-up or pull-down resistor (see please

DS)

X1*, X1A*

*Only for devices with subclk.

Oscillator output, the crystal and load capacitor must be connected with shortest distance and

without any vias.

If not used so shall be open

3.4 Power Line Routing

In general, the Vcc and Vss lines should not be routed in “chains”, but in “star shape”. For two layers board the Vss is

recommended as ground plane which covers the chip package, and is connected in one point to Vss of the whole circuit

to avoid a ground loop.

Below is a principal example of a bad and a good power line routing:

Figure 5. Example of bad vs. good power line routing

For four and more layers PCB the Vcc and Vss should be routed as a plane in the inner layers of PCB. Concerning the

layer stack the several Vdd power supply planes should be not overlapped in parallel layers to avoid noise coupling.

Recommendation for good EMC behaviour:

▪Use four layers or six layers PCB

▪Use power supply planes (ground and power) in the inner-layer of PCB layer stack

▪Reduce the distance between the power planes (low impedance)

▪One or two decoupling capacitors close to each VCC pad/pair to adjacent VSS-pad/pair (route under).

▪Use capacitor groups to match frequency behaviour of power supply decoupling. The decoupling capacitors can

have values between 1 nF and 10 µF.

▪Use ferrite filter for each power domain

▪Split the used I/O signals in separate layer for low / high speed, and digital / analog signal types

Recommendation for Hardware Setup 32-Bit FR81S Family

www.cypress.com Document No. 002-09375 Rev. *B 10

Below is an example for PCB layer stack:

Figure 6. Example of PCB layer stack

GND

AVcc

Vcc

low speed signals

high speed signals

BAD crosstalk between

different power supply

planes

GND

Avcc / Vcc

low speed signals

high speed signals

GOOD separation of

power supply planes for

low EMC requirements

3.5 Power Supply Decoupling

DeCaps for power supply have to be placed within the “current flow”. Otherwise they are senseless, because then their

function become inoperable. The following graphic illustrates this:

Figure 7. Power Supply decoupling caps placement

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