Design Gateway IP Lock Manuale utente
IP Lock (standard pack)
Users Manual
Design Gateway Co.,Ltd.
Rev 1.5
(PD0602-6-01-05E)
*** Please read this manual carefully before using IP Lock (standard pack)***
I
IP Lock (standard pack) Users Manual - I - P 0602-6-01-05E
evision History
Revision
ate etail of change
1.0 10 May 2006 Initial Release
1.1 18 July 2006 Adding IP lock core for Altera FPGA.
1.2 19 October 2006 Update detail of setting internal pull-up on ISE
Update detail of SC0 signal
1.3 8 November 2007 Support Xilinx Virtex5
Adding Troubleshooting
1.4 6 August 2010 Update Figure 4-1 and 4-8
1.5 15 October 2010 Update evice support
IP Lock (standard pack) Users Manual - II - P 0602-6-01-05E
Table of Contents
1.
Introduction .......................................................................................................................................1
1.1.
Summary Feature .....................................................................................................................1
1.2.
Minimum System Requirement.................................................................................................1
1.3.
Warranty Policy.........................................................................................................................2
1.4.
Customer Support ....................................................................................................................2
2.
IP Lock System .................................................................................................................................3
3.
IP Lock core ......................................................................................................................................4
3.1.
IP Lock core for Xilinx FPGA ....................................................................................................4
3.2.
IP Lock core for Altera FPGA ...................................................................................................4
4.
IP Lock evice ..................................................................................................................................6
5.
Example VH L design......................................................................................................................9
6.
Troubleshooting ..............................................................................................................................10
1
IP Lock (standard pack) Users Manual - 1 - P 0602-6-01-05E
1. Introduction
Thank you very much for purchasing IP Lock. Please check that all the following items are in the
box. If anything is missing or damaged, contact your distributor or esign Gateway Co.,Ltd.
1. IP Lock device 10 or 50 pcs.
2. Users manual
3. C ROM contains :
-IP Lock users manual (IPL_UserManual1_1_E.pdf)
-IP Lock core for Xilinx (TopIPLock.vhd, iplock.ngc and iplockex.ngo)
-IP Lock core for Altera (TopIPLock.vhd, iplock.vhd)
-Example VH L design source codes (Counter.vhd, Counter32Bits.vhd)
1.1. Summary Feature
1. 128-bit AES encryption
2. IP Lock core and IP Lock device sent and receive data for checking every 200 msec
3. Xilinx FPGA support only Spartan2, Spartan2E, Spartan3, Spartan3E, Spartan6, Virtex, Virtex2,
Virtex2Pro, Virtex4, Virtex5 and Virtex6
4. Altera FPGA support only Stratix, Stratix2, Stratix3, Stratix4, ArriaGX, Arria2GX, Cyclone
Cyclone2 and Cyclone3
1.2. Minimum System Requirement
1. Pentium III or compatible processor
2. RAM 256 MB
3. Windows XP
4. Xilinx ISE 7.1 or over for Xilinx FPGA designer
5. Quartus II 4.1 or over for Altera FPGA designer
IP Lock (standard pack) Users Manual - 2 - P 0602-6-01-05E
1.3. Warranty Policy
1. Product warranty is valid for 1 year from purchasing date.
2. Warranty is void if any modification has been made to this product and any incorrect operation
from this manual or warranty sticker is torn or damaged.
3. In order to claim for product exchange or technical support within warranty period, official
receipt is required for unregistered customer as an evidence of purchasing whereas official
receipt is unnecessary for registered customer (please fill up registration card attached
herewith the product and send back to esign Gateway Co.,Ltd).
1.4. Customer Support
Customer can contact to support@design-gateway.com for support of any problem about IP Lock
or visit our website at www.design-gateway.com.
Your Personal information will be restricted with high confidentiality.
IP Lock (standard pack) Users Manual - 3 - P 0602-6-01-05E
2. IP Lock System
Figure 2-1 IP Lock System
From above block diagram, it is shown IP Lock system. IP Lock core communicate with IP Lock
device for check users key. If users key is correct, ENABLE signal is logic 1 (enable). On the other
hand, if users key is not correct, ENABLE signal is logic 0 (disable). User can use ENABLE signal
from IP Lock core to enable users logic. For IP Lock (standard pack) Design Gateway Co.,Ltd fi
user#s key in IP Lock core and IP Lock device so user can not change user#s key value. And each IP
Lock (standard pack) users key value is not same value so user can not use IP Lock core and IP Lock
device from different standard pack.
IP Lock core use 3 signals for active. That is SC0, C0 and 0. SC0 signal is system clock for IP
Lock core. It use internal clock from users logic but SC0 must have frequency range between 1-25
MHz. C0 and 0 signal is data signal. It use for communicate between IP Lock core and IP Lock
device.
Because ENABLE signal from Top IP Lock does not synchronous with users clock so user should
be add a Flip-Flop in users logic as show in Figure 2-2. ENABLE signal that out from Flip-Flop is
synchronous with users clock in users logic.
Figure 2-2 Recommend logic on ENABLE signal
Top Level of users logic
FPGA
Top IP Lock
IP Lock device
Users Logic
ENABLE
0
C0
SC0
Users Logic
-Flip Flop
ENABLE
(from Top
IP
Lock)
ENABLE
Users Clock
Clk
Q
IP Lock (standard pack) Users Manual - 4 - P 0602-6-01-05E
3. IP Lock core
3.1. IP Lock core for Xilinx FPGA
Figure 3-1 Top level of IP Lock for Xilinx FPGA
Figure 3-1 shows block diagram of top level IP Lock for Xilinx FPGA.
-Xilinx IP Lock core (iplock.ngc and iplockex.ngo): IP Lock core communicate with IP Lock
device for check users key before enable ENABLE signal. If communication between IP
Lock core and IP Lock device failed or users key is not same value, IP Lock will disable
ENABLE signal.
-User must copy iplock.ngc and iplockex.ngo to Xilinx project folder before start synthesis
and implement H L code.
-Users key value already fix in IP Lock core.
3.2. IP Lock core for Altera FPGA
Figure 3-2 Top level of IP Lock for Altera FPGA
IP Lock core
(iplock.vhd)
Users key fix in IP Lock core
ENAB
L
E
SC0
C0
0
Top IP Lock (TopIPLock.vhd)
IP Lock core
(iplock.ngc & iplockex.ngo)
Users key fix in IP Lock core
ENAB
L
E
SC0
C0
0
Top IP Lock (TopIPLock.vhd)
IP Lock (standard pack) Users Manual - 5 - P 0602-6-01-05E
Figure 3-2 shows block diagram of top level IP Lock for Altera FPGA.
-Altera IP Lock core (iplock.vhd): IP Lock core communicate with IP Lock device for check
users key before enable ENABLE signal. If communication between IP Lock core and IP
Lock device failed or users key is not same value, IP Lock will disable ENABLE signal.
-Users key value already fix in IP Lock core.
-User must add IP Lock license into Quartus II license as shown in Figure 3-3 before start
synthesis and implement H L code. If user does not have IP Lock license, User can not
synthesis and implement IP Lock core.
-IP Lock license file: User must send email to iplock@design-gateway.com for request IP
Lock license and esign Gateway Co.,Ltd require some information for register as shown
in Figure 3-4. Please fill this information in email.
-User can check Volume Serial Number by run OS prompt and use command dir on
window drive as shown in Figure 3-5 .
Figure 3-3 IP Lock license in Quartus II license
IP Lock (standard pack) Users Manual - 6 - P 0602-6-01-05E
Figure 3-4 Information for register
Figure 3-5 Volume Serial Number
4. IP Lock Device
IP Lock device is device, which communicates with IP Lock core, for protect FPGA core. IP Lock
device must connect to FPGA (IP Lock core) all time. Figure 4-1 shows recommend schematic of IP
Lock device. Voltage I/O of FPGA that connects to IP Lock device should be connecting to +3.3 - +5 V.
Figure 4-1 Schematic of IP Lock evice
For Xilinx FPGA, user can use internal pull up in FPGA by
-setting in esign Object List I/O Pins on ISE as shown in Figure 4-2
or
-edit ucf file (User Constraint File) of users logic as shown in Figure 4-3.
Na
me /
Company
:
..
IP Lock Serial Number:
Volume Serial Number: ....................................
Address: .
Tel: ...
Fax: .....
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