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Document Number DS39933 Rev 2-2

PI7C9X2G304SL

PCI EXPRESS GEN 2 PACKET SWITCH

3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch

DATASHEET

REVISION 2-2

September 2017

1545 Barber Lane Milpitas, CA 95035

Telephone: 408-232-9100

FAX: 408-434-1040

Internet: http://www.di o de s .c om

PI7C9X2G304SL Page 3 of 88 September 2017

Document Number DS39933 R ev 2-2 w ww.diodes .com© Diodes Incorpor ated

PI7C9X2G304SL

IM PORTANT NOTICE

DIO DES INCO RPORA T ED MA K ES NO WA RRA NTY OF A NY KIND, EX PR ES S OR IMPL IED, W ITH REGA RDS TO THIS

DO CUMENT, INCL UD ING, B U T N OT L IMIT ED TO, TH E IMPL IED WA RRA NTIES O F MERCHA NTA B IL ITY A ND F ITNESS FOR A

PA RTICULA R PURPOSE ( A ND THEIR EQUIV A LENTS UNDER THE LA WS OF A NY JURISDICTION) .

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other

changes w ithout f urther notice to this document and any product described herein. Diodes Incorporated does not assume any liability

arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any

license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described

herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies w hose

products are represented on Diodes Incorporated w ebsite, harmless against all damages.

Diodes Incorporated does not w arrant or accept any liability whatsoever in respect of any products purchased through unauthorized

sales channel.

Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall

indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.

Products described herein may be covered by one or more United States, international or foreign patents pending. Product names

and markings noted herein may also be covered by one or more United States, international or foreign trademarks.

This document is written in English but may be translated into multiple languages for ref erence. Only the English version of this

document is the final and determinative format released by Diodes Incorporated.

LIFE SUPPORT

Diodes Incorporated products are specifically not authorized f or use as critical components in life support devices or systems w ithout

the express w ritten approval of the Chief Executive Officer of Diodes Incorporated. As used herein:

A. Life support devices or systems are devices or systems w hich:

1. are intended to implant into the body, or

2. support or sustain life and w hose failure to perform w hen properly used in accordance w ith instructions for use provided

in the labeling can be reasonably expected to result in significant injury to the user.

B. A critical component is any component in a life support device or system w hose failure to perform can be reasonably expected to

cause the f ailure of the life support device or to affect its safety or effectiveness.

Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or

systems, and acknow ledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements

concerning their products and any use of Diodes Incorporated products in such saf ety-critical, life support devices or systems,

notw ithstanding any devices- or systems -related information or support that may be provided by Diodes Incorporated. Further,

Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes

Incorporated products in such safety-critical, life support devices or systems.

www. d i o de s . c o m

PI7C9X2G304SL Page 4 of 88 September 2017

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PI7C9X2G304SL

REVISION HISTORY

Date

Revision Number

Description

06/09/10

0.1

Preliminary Datasheet

10/21/10

0.2

Added Section 6 EEPROM Interface And System Management Bus

Added Section 7 Register Description

07/12/11

0.3

Added Industrial Temperature Support (Section 1 Features, Section 11.1 Absolute

M aximum Ratings, Section 13 Ordering Information)

11/23/11

0.4

Up dated Section 1 Features (integrated reference clock)

Updated Section 3.1 PCI Express Interface Signals (Added REFCLKI_P, REFCLKI_N,

REFCLKO_P[2:0], REFCLKO_N[2:0], and IREF)

07/25/12

1.0

Up dated Section 1 Features (OBFF and LTR support)

Updated Section 3 Pin Description (RXPOLINV_DIS, P RSNT [3:1], TEST4,TEST5, and

CVDDR)

Up dated Section 6 EEPROM Interface And Sy stem M anagement Bus

Up dated Section 7 Register Description

01/02/13

1.1

Updated Section 3 Pin Description (PWR_SAV, TCK, and TRST_L)

Added Section 11.4 AC Switching Characteristics of Clock Buffer

Up dated Table 8-1 Clock Requirement

Updated Table 3.5 Power Pins

Updated Table 4.1 Pin List of 129-Pin LQFP

07/15/14

1.2

Updated Section 1 (512-by te maximum p ayload size support, No-blocking cap ability )

Up dated Section 3.2 Port Configuration Signals

Up dated Section 3.3 M iscellaneous Signals

Updated Section 4.1 Pin List of 129-Pin LQFP

Updated Section 5.1 Physical Layer Circuit

Updated Section 5.1.7 Drive De-Emphasis

Updated Section 7.2.75 Device Capabilities Register (M ax_Payload_Size Supported)

Updated Section 13 Ordering Information

Up dated Table 11-2 DC Electrical Characteristics

11/17/14

1.3

Updated Section 7.2 Transparent M ode Configuration Regis t ers

Up dated Section 8 Clock Scheme

07/16/15

1.4

Up dated Section 3.1 PCI Express Interface Signals

Up dated Section 3.2 Port Configuration Signals

Updated Section 5.1 Physical Layer Circuit

Updated Section 6.1 EEPROM Interface

Up dated Section 7.2 Transparent M ode Configuration Registers

Up dated Section 8 Clock Scheme

Up dated Table 9-1 Instruction Register Codes

Up dated Table 9-2 JTAG Device ID Register

Up dated Table 9-3 JTAG Boundary Scan Register Definition

Up dated Table 11-2 DC Electrical Characteristics

09/07/15

1.5

Up dated Table 11-1 Absolute M aximum Ratings

12/23/15

1.6

Up dated Section 3.1 PIN Description

Up dated the Table 11-1 Absolute M aximum Ratings

Up dated the Table 11-2 DC Electrical Characteristics

03/04/16

1.7

Added Section 11

Power Sequence

Updated Section 4.1 PIN LIST of 129-PIN LQFP

09/05/17

2-2

Up dated Section 1 Features

Updated Section 3.2 Port Configuration Signals

Updated Section 5.1 Physical Layer Circuit

Updated Section 6.1.4 M appingEEPROM Contents to Configuration Registers

Updated Section 7.2 Transparent Mode Configuration Registers

Updated Section 12.1 Absolute M aximum Ratings

Up dated Table 12-2 DC Electrical Characteristics

Added Section 12.4 Operating Ambient Temperature

Added Section 12.5 Power Consumption

Revision numbering system changed to whole number

PI7C9X2G304SL Page 5 of 88 September 2017

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PI7C9X2G304SL

TABLE OF CONTENTS

1FEA T U R ES ....................................................................................................................................................................................... 10

2GENERAL DESCRIPTION......................................................................................................................................................... 11

3PIN DESCRIPTION ....................................................................................................................................................................... 13

3.1 PCI EX P R ES S INTERFACE SIGNA LS ....................................................................................................................13

3.2 PORT CONFIGURATION SIGNA LS ........................................................................................................................14

3.3 MISCELLANEOUS SIGNA LS....................................................................................................................................14

3.4 JTA G BOUNDARY SCA N SIGNA LS .......................................................................................................................15

3.5 POW ER PINS ..................................................................................................................................................................16

4PIN ASSIGNMENTS ...................................................................................................................................................................... 17

4.1 PIN LIST OF 129-PIN LQFP .........................................................................................................................................17

5FUNCTIONAL DESCRIPTION................................................................................................................................................. 18

5.1 PHYS ICA L LA YER CIRCUIT ....................................................................................................................................18

5.1.1 RECEIVER DETECTION .................................................................................................................................18

5.1.2 RECEIVER SIGNAL DETECTION .................................................................................................................19

5.1.3 RECEIVER EQUALIZATION ..........................................................................................................................19

5.1.4 TRANSMITTER S WING ....................................................................................................................................19

5.1.5 DRIVE AMPLITUDE AND DE-EMPHASIS SETTINGS ............................................................................19

5.1.6 DRIVE AMPLITUDE.........................................................................................................................................20

5.1.7 DRIVE DE-EMPHASIS .....................................................................................................................................21

5.1.8 TRANSMITTER ELECTRICAL IDLE LATENCY .........................................................................................21

5.2 DATA LI N K LA YER (DLL) ........................................................................................................................................21

5.3 TRANSACTION LA YER RECEIVE BLOCK (TLP DECAPSULATION) ........................................................22

5.4 ROUTING ........................................................................................................................................................................22

5.5 TC/ VC MAPPING ..........................................................................................................................................................22

5.6 QUEUE.............................................................................................................................................................................22

5.6.1 PH .........................................................................................................................................................................23

5.6.2 PD .........................................................................................................................................................................23

5.6.3 NPHD ...................................................................................................................................................................23

5.6.4 CPLH ....................................................................................................................................................................23

5.6.5 CPLD ....................................................................................................................................................................23

5.7 TRANSACTION ORDERING.....................................................................................................................................23

5.8 PORT ARBITRATION..................................................................................................................................................24

5.9 VC A RBIT RATIO N .......................................................................................................................................................24

5.10 F LOW CONTROL..........................................................................................................................................................24

5.11 TRANSATION LA YER TRANSMIT BLOCK (TLP ENCAPSULATION) .......................................................25

5.12 ACCE SS CONTROL SERVICE............................................................................................................................................25

6EEP RO M IN TERFACE AND SYSTEM MANAGEMENT BUS...................................................................................... 26

6.1 EEPROM INT ERFA CE .................................................................................................................................................26

6.1.1 AUTO M ODE EERPOM ACCESS ..................................................................................................................26

6.1.2 EEPROM MODE AT RESET ...........................................................................................................................26

6.1.3 EEPROM SPACE ADDRESS MAP.................................................................................................................26

6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ...............................................28

6.2 SMBU S INT ERFA CE .....................................................................................................................................................36

7REGISTER DESCRIPTION........................................................................................................................................................ 37

7.1 REGISTER T YP ES .........................................................................................................................................................37

7.2 TRANSPARENT MODE CONFIGURATION REGISTERS ................................................................................37

PI7C9X2G304SL Page 6 of 88 September 2017

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7.2.1 VENDOR ID REGISTER – OFFSET 00h ......................................................................................................39

7.2.2 DEVICE ID REGISTER – OFFSET 00h........................................................................................................39

7.2.3 COMMAND REGISTER – OFFSET 04h .......................................................................................................39

7.2.4 PRIMARY STATUS REGISTER – OFFSET 04h...........................................................................................40

7.2.5 REVISION ID REGISTER – OFFSET 08h ....................................................................................................41

7.2.6 CLASS CODE RE GISTE R – OFFSET 08h....................................................................................................41

7.2.7 CACHE LINE REGISTER – OFFSET 0Ch....................................................................................................41

7.2.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................................................41

7.2.9 HEADER TYPE REGISTER – OFFSET 0Ch ................................................................................................41

7.2.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h...............................................................................41

7.2.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................41

7.2.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h....................................................................42

7.2.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ..................................................................42

7.2.14 I/O BASE ADDRESS REGISTER – OFFSET 1Ch .......................................................................................42

7.2.15 I/O LIM IT A DDRESS RE GISTER – OFFSET 1Ch ......................................................................................42

7.2.16 SECONDARY STATUS REGISTER – OFFSET 1Ch ...................................................................................42

7.2.17 MEMORY BASE ADDRESS REGISTER – OFFSET 20h............................................................................43

7.2.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ..........................................................................43

7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h..........................................43

7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ........................................43

7.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ..........44

7.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ........44

7.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.........................................................44

7.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................................44

7.2.25 CAPABILITY POINTER REGISTER – OFFSET 34h ..................................................................................44

7.2.26 INTERRUPT LINE REGISTER – OFFSET 3Ch...........................................................................................45

7.2.27 INTERRUPT PIN REGISTER – OFFSET 3Ch .............................................................................................45

7.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch ........................................................................................45

7.2.29 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 40h ......................................................46

7.2.30 POWER MANAGEMENT DATA REGISTER – OFFSET 44h ...................................................................46

7.2.31 PPB SUPPORT EXTENSIONS – OFFSET 44h............................................................................................47

7.2.32 DATA REGISTER – OFFSET 44h...................................................................................................................47

7.2.33 MSI CAPABILITY REGISTER – OFFSET 4Ch (Downstream Port Only)...............................................47

7.2.34 MESSAGE CONTROL REGISTER – OFFSET 4Ch (Downstream Port Only).......................................47

7.2.35 MESSAGE ADDRESS REGISTER – OFFSET 50h (Downstream Port Only) ........................................47

7.2.36 MESSAGE UPPER ADDRESS REGISTER – OFFSET 54h (Downstream Port Only) .........................48

7.2.37 MESSAGE DATA REGISTER – OFFSET 58h (Downstream Port Only) ................................................48

7.2.38 VPD CAPABILITY REGISTER – OFFSET 5Ch (Upstream Port Only)...................................................48

7.2.39 VPD DATA REGISTER – OFFSET 60h (Upstream Port Only) ................................................................48

7.2.40 VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h ..............................................................48

7.2.41 XPIP CSR0 – OFFSET 68h (Test Purpose Only).........................................................................................49

7.2.42 XPIP CSR1 – OFFSET 6Ch (Test Purpose Only) ........................................................................................49

7.2.43 REPLAY TIME-OUT C OUNTER – OFFSET 70h........................................................................................49

7.2.44 ACKNOWLEDGE LATENCY TIMER – OFFSET 70h................................................................................49

7.2.45 SWITCH OPERATION MODE – OFFSET 74h (Upstream Port).............................................................50

7.2.46 SWITCH OPERATION MODE – OFFSET 74h (Downstream Port)........................................................51

7.2.47 XPIP_CSR2 – OFFSET 78h.............................................................................................................................51

7.2.48 PHY PARAMETER 1 – OFFSET 78h.............................................................................................................51

7.2.49 PHY PARAMETER 2 – OFFSET 7Ch ............................................................................................................52

7.2.50 XPIP_CSR3 – OFFSET 80h.............................................................................................................................52

7.2.51 XPIP_CSR4 – OFFSET 84h.............................................................................................................................52

7.2.52 XPIP_CSR5 – OFFSET 88h.............................................................................................................................53

7.2.53 TL_CSR – OFFSET 8Ch ...................................................................................................................................53

7.2.54 PHY PARAMETER 3 – OFFSET 90h.............................................................................................................54

7.2.55 PHY PARAMETER 4 - OFFSET 94h..............................................................................................................54

7.2.56 OPERA TION M ODE –OFFSET 98h..............................................................................................................54

PI7C9X2G304SL Page 7 of 88 September 2017

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PI7C9X2G304SL

7.2.57 SSID/SSVID CAPABILITY REGISTER – OFFSET B0h..............................................................................54

7.2.58 SUBSYSTEM ID REGISTER – OFFSET B4h ...............................................................................................55

7.2.59 GPIO C ONTR OL REGISTER – OFFSET B8h (Upstream Port Only).....................................................55

7.2.60 EEPROM CONTROL REGISTER – OFFSET BCh (Upstream Port Only).............................................56

7.2.61 EEPROM ADDRESS REGISTER – OFFSET BCh (Upstream Port Only)..............................................57

7.2.62 EEPROM DATA REGISTER – OFFSET BCh (Upstream Port Only)......................................................57

7.2.63 PCI EXPRESS CAPABILITY REGISTER – OFFSET C0h .........................................................................57

7.2.64 DEVICE CAPABILITIES REGISTER – OFFSET C4h ................................................................................58

7.2.65 DEVICE CONTROL REGISTER – OFFSET C8h........................................................................................58

7.2.66 DEVICE STATUS REGISTER – OFFSET C8h.............................................................................................59

7.2.67 LINK CAPABILITIES REGISTER – OFFSET CCh .....................................................................................60

7.2.68 LINK C ONTROL REGISTER – OFFSET D0h..............................................................................................61

7.2.69 LINK STATUS R EGISTER – OFFSE T D0h ..................................................................................................61

7.2.70 SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET D4h .......................................62

7.2.71 SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET D8h................................................63

7.2.72 SLOT STATUS REGISTER (Downstream Port Only) – OF FSET D8h ....................................................64

7.2.73 DEVICE CAPABILITIES REGISTER 2 – OFFSET E4h .............................................................................64

7.2.74 DEVICE CONTROL REGISTER 2 – OFFSET E8h .....................................................................................64

7.2.75 DEVIDE STATUS REGISTER 2 – OFFSET E8h .........................................................................................65

7.2.76 LINK CAPABILITIES REGISTER 2 – OFFSET ECh..................................................................................65

7.2.77 LINK C ONTROL REGISTER 2 – OFFSET F0h ...........................................................................................65

7.2.78 LINK STATUS R EGISTER 2 – OFFSET F0h................................................................................................65

7.2.79 SLOT CAPABILITIES REGISTER 2 – OFFSET F4h ..................................................................................65

7.2.80 SLOT C ONTOR L REGISTER 2 – OFFSET F8h ..........................................................................................65

7.2.81 SLOT S TATUS REGISTER 2 – OFFSET F8h ...............................................................................................66

7.2.82 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER – OFFSET 100h.......66

7.2.83 UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .......................................................66

7.2.84 UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h...........................................................67

7.2.85 UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ..................................................67

7.2.86 CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h ............................................................68

7.2.87 CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h................................................................69

7.2.88 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h............................69

7.2.89 HEADER LOG REGISTER – OFFSET From 11Ch to 128h......................................................................70

7.2.90 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER – OFFSET 140h................................70

7.2.91 PORT VC CAPABILITY REGISTER 1 – OFFSET 144h.............................................................................70

7.2.92 PORT VC CAPABILITY REGISTER 2 – OFFSET 148h.............................................................................70

7.2.93 PORT VC C ONTROL REGISTER – OFFSET 14Ch....................................................................................71

7.2.94 PORT VC STATUS REGISTER – OFFSET 14Ch ........................................................................................71

7.2.95 VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h...............................................................71

7.2.96 VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h...................................................................72

7.2.97 VC RESOURCE STATUS REGISTER (0) – OFFSET 158h .......................................................................72

7.2.98 VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch..............................................................73

7.2.99 VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h...................................................................73

7.2.100 VC RESOURCE STATUS REGISTER (1) – OFFSET 164h .......................................................................74

7.2.101 VC ARBITRATION TABLE REGISTER – OFFSET 170h...........................................................................74

7.2.102 PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h..............................74

7.2.103 PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER – OFFSET 20Ch.............................75

7.2.104 DATA SELECT REGISTER – OFFSET 210h................................................................................................75

7.2.105 POWER BUDGETING DATA REGISTER – OFFSET 214h......................................................................75

7.2.106 POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ................................................................76

7.2.107 ACS EXTENDED CAPABILITY HEADER – OFFSET 220h (Downstream Port Only)........................76

7.2.108 ACS CAPABILITY REGISTER – OFFSET 224h (Downstream Port Only).............................................76

7.2.109 EGRESS CONTROL VECTOR – OFFSET 228h (Downstream Port Only) ............................................77

7.2.110 LTR EXTENDED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only).............................77

7.2.111 MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only).......................................77

7.2.112 MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only)...............................77

PI7C9X2G304SL Page 8 of 88 September 2017

PI7C9X2G304SL

8CLOCK S C H EM E .......................................................................................................................................................................... 79

9IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.......................................................................................................... 80

9.1 INST RU CT IO N REGISTER.........................................................................................................................................80

9.2 BYPASS REGISTER .....................................................................................................................................................80

9.3 DEVICE ID REGISTER ................................................................................................................................................80

9.4 BOUNDA RY S CAN REGISTER ................................................................................................................................81

9.5 JTA G BOUNDARY SCAN REGISTER ORDER.....................................................................................................81

10 POWER MANAGEMENT ........................................................................................................................................................... 83

11 POWER SEQUENCE..................................................................................................................................................................... 84

12 ELECTRICAL AND TIMING SPECIFICATIONS.............................................................................................................. 85

12.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................85

12.2 DC SPECIFICATIONS ..................................................................................................................................................85

12.3 AC SPECIFICAT IONS ..................................................................................................................................................85

12.4 OPERATING AM BI ENT TEMPERATURE.............................................................................................................87

12.5 POW ER CONSUMPTION............................................................................................................................................87

13 PACKAGE INFORMATION....................................................................................................................................................... 88

14 ORDERING INFORMATION .................................................................................................................................................... 89

PI7C9X2G304SL Page 9 of 8September 2017

PI7C9X2G304SL

TABLE OF FIGURES

FI GURE 5-1 DRIVER OUTPUT WAVEFORM.....................................................................................................................................20

FI GURE 6-1 SMBU S ARCHIT ECTURE IMPLEMENTATION ON PI7C9X2G304SL.......................................................................36

FI GURE 11-1 INITIAL POWER-UP SEQUENCE.................................................................................................................................84

FI GURE 13-1 PACKAGE OUTLINE DRAWING...................................................................................................................................88

LIST OF TABLES

TABLE 5-1 RECEIVER DETECTION THRESHOLD SETTINGS..........................................................................................................18

TABLE 5-2 RECEIVER SIGNAL DETECT THRESHOLD....................................................................................................................19

TABLE 5-3 RECEIVER EQUALIZATION SETTINGS..........................................................................................................................19

TABLE 5-4 TRANSMITTER SWI NG SETTINGS..................................................................................................................................19

TABLE 5-5 DRIVE AMP LIT UDE BA SE LEVEL REGISTERS.............................................................................................................20

TABLE 5-6 DRI VE AMP LIT UDE BA SE LEVEL SETTINGS...............................................................................................................20

TABLE 5-7 DRI VE DE-EM P H A SI S BA SE LEVEL REGI ST E R ...........................................................................................................21

TABLE 5-8 DRI VE DE-EM P H A SI S BA SE LEVEL SETTINGS ...........................................................................................................21

TABLE 5-9 SUMMARY OF PCI EX P RE SS ORDERING RULES.........................................................................................................23

TABLE 6-1 SMBU S AD D RE SS PIN CONFIGURATION.....................................................................................................................36

TABLE 7-1 REGI STER ARRAY LAYOUT FOR VC ARBIT RATION..................................................................................................74

TABLE 7-2 TABLE ENT RY SIZ E I N 4BIT S.......................................................................................................................................74

TABLE 8-1 AC SW IT CHI N G CHARACTERISTICS.............................................................................................................................79

TABLE 9-1 INSTRUCTION RE GI ST ER CODES...................................................................................................................................80

TABLE 9-2 JTA G DEVICE ID REGISTER.........................................................................................................................................80

TABLE 9-3 JTA G BOUNDARY SCAN REGISTER DEFINITION.......................................................................................................81

TABLE 12-1 ABSOLUTE MAXIMUM RAT I N GS................................................................................................................................85

TABLE 12-2 DC ELECTRICAL CHARACTERISTICS.........................................................................................................................85

TABLE 12-3 PCI EX P RE SS INTERFACE -DIFFERENT IAL TRANSMITTER (TX) OUT PUT (5.0 GBP S)CHARACTERIST ICS .....85

TABLE 12-4 PCI EX P RE SS INTERFACE -DIFFERENT IAL TRANSMITTER (TX) OUT PUT (2.5 GBP S)CHARACTERIST ICS .....86

TABLE 12-5 PCI EX P RE SS INTERFACE -DIFFERENT IAL RECEIVER (RX) INP UT (5.0 GBP S)CHARACT ERIST ICS ................86

TABLE 12-6 PCI EX P RE SS INTERFACE -DIFFERENT IAL RECEIVER (RX) INP UT (2.5 GBPS)CHARACT ERIST ICS ................87

TABLE 12-7 OP ERAT ING AMBIENT TEMPERATURE......................................................................................................................87

TABLE 12-8 POWER CONSUMPTION................................................................................................................................................87

PI7C9X2G304SL Page 10 of 9September 2017

PI7C9X2G304SL

1FEAT URES

•4-lane PCI Express Ge n 2 Switch with 3 PCI Express ports

•Supports “Cut-through”(Default) as well as “Store and Forward” mode for packet s witching

•Peer-to-peer switching between any two downstream ports

•150 ns typical latency for packet routed through Switch without blocking

•Integrated reference clock for downstream ports

•Strapped pins configurable with optional EEPROM or SMBus

•SMBus interface support

•Compliant with SystemManagement (SM) Bus, Version 1.0

•Compliant with PCI Express Base Specification Revision 2.1

•Compliant with PCI Express CEM Specification Revision 2.0

•Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2

•Compliant with Advanced Configuration PowerInterface (ACPI) Specification

•Reliability, Availability and Serviceability

-Supports Data Poisoning and End-to-End CRC

-Advanced Error Reporting and Logging

-IEEE 1149.1 JTAG interface support

•Advanced Power Saving

-Empty downstreamports are set to idle state to minimize power consumption

•Link Power Management

-Su p ports L0, L0s , L1, L2, L2/L3Ready and L3 link power states

-Active state power management for L0s and L1 states

•Device State Power Management

-Supports D0, D3Hot and D3Cold device power states

-3.3V Aux Power support in D3Cold power state

•Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR

•Extended Virtual Channel capability

-Two Virtual Channels (VC) and Eight Traffic Class (TC) support

-Dis abled VCs’ buffer is assigned to enabled VCs for resource sharing

-Independent TC/VC mapping for each port

-Provides VC arbitration selections: Strict Priority, Round Robin (RR) and Programmable Weighted

•Supports Isochronous Traffic

-Isochronous traffic class mapped to VC1 only

-Strict time based credit policing

•Supports up to 512-b y t e ma ximu m payload s ize

•Programmable driver current and de-emphasis level at each individual port

•Support Access Control Service (ACS) for peer-to-peer traffic

•Support Address Translation (AT) packet for SR-IOV application

•Support OBFF and LTR

•Low Power Dissipation: 650 mW typical in L0 normal mode

•Industrial Temperature Range -40oto 85oC

•128-pin LQFP 14mm x 14mm package

PI7C9X2G304SL Page 11 of 10 September 2017

PI7C9X2G304SL

2GENERAL DESCRIPTION

Similar to the role o f PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to

expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect

architecture. The 4-lane PCIe Switch is in 3-port type configuration. It provides users the flexibility to expand or

fan-out the PCI Express lanes based on their application needs.

In the PCI Exp ress Architecture, the PCI E Switch forwards posted and non-posted requests, and completion packets

in e ither downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port.

By vis ualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual

PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a P CI Bridge

during enumeration, each port is given a unique bus number, device number, and function number by the initiating

software. The bus number, device number, and function number are combined to form a destination ID for each

specific port. In addition to that, the memory-map and IO address ranges are exclu s ively allocated to each port as

well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded

address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the

packets to multiple s mall packets or merge the received packets into a large transmit packet. A ls o, the IDs of the

requesters and completers are kept unchanged along the path between ingress and egress port.

The Switch emp loys the architecture of Combined Input and Output Queue (CIOQ) in implementation.

The main reason for choosing CIOQ is that the required me mo ry bandwidth of input queue equals to the bandwidth of

ingress port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at

each ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port

bas ed on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass

over each other in case that the addressed egress port is available to accept them. As to the packets required to follow

the ordering rule, the Head-Of-Line ( HO L) is s ue becomes unavoidable for packets destined to different egress ports

since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up

problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it

out. This can assure the maximum throughput being achieved and therefore the Switch wo rks effic iently. Another

advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified and

streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port maintains

the credits independently without checking other ports' credit availability, which is otherwise required by pure output

queue architecture.

The Switch supports two virtual channels (VC0, VC1) and eight traffic classes (TC0 ~ TC7) at each port.

The ingress port independently assigns packets into the preferred virtual channel while the egress port outputs the

packet based on the predefined port and VC arbitration algorithm. For instance, the isochronous packet is given a

special traffic class number other than TC0 and mapped into VC1 accordingly. By employing the strict time based

credit policy for port arbitration and assigning higher priority to VC1 than VC0, the Switch can therefore guarantee

the time-s ens itiv e packet is not blocked by regular traffic to assure the quality of service. In addition, some data-

centric applications only carry TC0/VC0 t raffic. As a result, there are no packets that would consume VC1 bandwidth.

In order to improve the efficiency of buffer usage, the unused VC1 queues can be reassigned to VC0 and enable each

of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the

performance of the PCIe Switch further.

The Switch provides the advanced feature of Access Control Service (ACS). This feature regulates which components

are allowed to communicate with each other within the PCIe mu ltip le-point fabric, and allows the system to have

more control over packet routing in the Switch. As a result, peer-to-peer traffic can be facilitated more accurately and

efficiently. When the system also implements Address Translation Service (ATS), the peer-to-peer requests with

translated address can be routed directly by enabling the corresponding option in ACS to avoid possible performance

bottleneck associated with re-direction, which introduces extra latency and may increase link and RC congestion.

The built-in Integrated Reference Clock Buffer of the PCI Exp res s Switch supports three reference clock outputs.

The clock buffer is froma single 100MHz clock input, and distributes the clock source to three outputs, which can be