Dynamic Engineering LVDS 8R Manuale utente
Hardware and Software Design • Manufacturing Services
page 1
PCI LVDS 8R
8 Channel LVDS Serial Interface
Dynamic Engineering
435 Park Drive, Ben Lomond, CA 95005
831-336-8891
www.dyneng.com
10-2001-0202
This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or
reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the
purpose for which it was delivered.
Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the
company reserves the right to make improvements or changes in the product described in this document at any
time and without notice. Furthermore, Dynamic Engineering assumes no liability arising out of the application or
use of the device described herein.
The electronic equipment described herein generates, uses, and can radiate radio frequency energy. Operation of
this equipment in a residential area is likely to cause radio interference, in which case the user, at his own
expense, will be required to take whatever measures may be required to correct the interference.
Dynamic Engineering’s products are not authorized for use as critical components in life support devices or
systems without the express written approval of the president of Dynamic Engineering.
This product has been designed to operate with PCI and compatible user-provided equipment. Connection of
incompatible hardware is likely to cause serious damage.
©2000,2001,2002 by Dynamic Engineering.
Manual Revision E. Revised 4/4/02
Hardware and Software Design • Manufacturing Services
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Table of Contents
Introduction 4
Memory Map 7
DMA Definitions 13
DMA Base Control 13
DMA Status 16
DMA FIFO Holding Register Target Read 17
DMA FIFO Holding Register DMA Read 18
DMA Xilinx Status 19
Address Generator Definitions 20
Address Generator SDRAM Start Address Registers 20
Address Generator SDRAM Length Registers 21
Address Generator SDRAM Control Registers 22
Address Generator SDRAM Base Control Registers 25
Address Generator SDRAM Status Registers 27
FE Definitions 29
FE Tag Bit Definition Registers 29
FE X Stop Registers 32
FE Y Stop Registers 32
FE Z Stop Registers 33
FE X Total Counter Read-back 33
FE Data Holding Register 34
FE Data Write Register 34
FE Channel Done 35
FE Pre-load Counter 36
Hardware and Software Design • Manufacturing Services
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Operational Brief: 37
LVDS Connector Definition 40
Construction and Reliability 43
Thermal Considerations 43
Warranty and Repair 43
Service Policy 44
Out of Warranty Repairs 44
For Service Contact: 44
Specifications 45
Order Information 46
Hardware and Software Design • Manufacturing Services
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Introduction
The PCI_LVDS_8R features 8 channels of LVDS input. Each input channel is composed of 3 serial data pairs plus a
reference clock. The reference clock can operate at speeds up to 175 MHz. The National DS90CR218 [TIA/EIA-
644] or equivalent receiver chip is used. The receiver converts the three parallel streams into 21 bit parallel
data. The PCI_LVDS_8R implements the lower two serial streams for a 14 bit parallel interface. The upper serial
stream and corresponding upper 7 bits are defined and routed to allow for future expansion and alternate
protocols to be implemented.
The LVDS channels are grouped two per Front End [FE] Xilinx. The FE Xilinx receives the data and performs data
filtering to allow programmed patterns to start capture and other patterns to be stored. The Data width is built
up from 14 to 16 bits with the addition of parity. The data samples are combined to form 32 bit words before
being written to the Input FIFO. There is one Input FIFO per LVDS channel. 1K x 32.
One Latch Xilinx handles 4 LVDS channels – the output from two FE Xilinx. The data is read from the Input FIFO by
the Latch Xilinx and either written to the SDRAM or to the Output FIFO. The data is read into the Latch Xilinx at 66
MHz and written to the SDRAM at 33 MHz. The data width is doubled from 32 bits to 64 bits in this path. The
Data can also be read from the SDRAM and written to the Output FIFO. When data is written to the Output FIFO
the width is 32 bits and the rate is 66 MHz. The Address Generator controls the Latch Xilinx and the SDRAM.
The data from the output FIFO can be read directly or as a DMA stream.
The Address Generator is used to control the Latch Xilinx [data path], and provide the address control for the
SDRAM. After Power-Up the Address Generator provides the control words to the SDRAM to initialize operation
and then the proper control sequences for refresh and burst access. In Capture mode the Address Generator
polls the Input FIFOs for data to be transferred into the SDRAM. When a FIFO’s Half-Full flag is set, data is
transferred from the FIFO through the Latch Xilinx into the SDRAM. In Retrieve mode the data is read from the
SDRAM and loaded into the Output FIFO. The Output FIFO is polled to see if there is room for the next burst of
data. In Direct mode the data is moved from the Input FIFO through the Latch Xilinx to the Output FIFO without
using the SDRAM.
Hardware and Software Design • Manufacturing Services
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The Data in the Output FIFO passes through the DMA Xilinx before the PLX [PCI interface] has access. The data is
written into the Output FIFO at 66 MHz and read out at 33 Mhz. The interface supports DMA and target reads.
The 2:1 load to read bandwidth insures rapid and efficient data transfer in Retrieve mode.
The FE design includes a software write path and load register to allow the software to load data words into the
Input FIFO directly. The FE design also has a 12 bit counter that can be used to load data automatically into the
FIFO for performance testing. The Counter inserts data at 33MHz. into the data path to provide a continuous data
stream. The counter can be used to cause Direct or Capture mode operations. Retrieve can be used after
capture to read the data back for test and development purposes.
The hardware as of this revision has all Channels and all data paths tested. An 8 channel LVDS data simulator was
used with multiple patterns, speeds, and programming scenarios to check on all modes of operation.
Hardware and Software Design • Manufacturing Services
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LVDS IF
LVDS IF
LVDS IF
LVDS IF
FIFO
FIFO
FIFO
FIFO
SDRAM
64
32
256 MB
1K x 32
DMA Xilinx
Add Gen
Xilinx
LVDS IF
LVDS IF
LVDS IF
LVDS IF
SDRAM
32
1K x 32
LAT Xilinx
256 MB
LVDS IF
LVDS IF
LVDS IF
LVDS IF
FIFO
FIFO
FIFO
FIFO
SDRAM
64
FIFO
32
256 MB
Add Gen
Xilinx
LVDS IF
LVDS IF
SDRAM
64
32
256 MB
1K x 32
PLX 9054
PCI 33/32
FIFO
FE Xilinx
FE Xilinx
FE Xilinx
FE Xilinx
LAT Xilinx
Control Bus
Hardware and Software Design • Manufacturing Services
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Memory Map
(Addresses shown as byte)
Addresses are offsets from the PCI Base Address defined by the system and the PLX 9054. The PLX 9054
requests several BARs. The BAR associated with Space 0 is the base address for the internal PCI_LVDS_8R
hardware. The CardId = 9054. The VendorId = 10B5. The Local Space must be enabled by writing a 0x0001 to
Space_0_Base [PLX 9054 internal register]. The Interrupt must be enabled within the PLX for the interrupts
described within this document to reach the host. Please download the PLX 9054 manual for complete details.
Front End Filter Channels 0,1
Decode number Address offset Chip Definition
0 0000 FE01 TAG_DEF_0
0004 FE01 X0_STOP
0008 FE01 X1_STOP
000C FE01 Y0_STOP
0010 FE01 Y1_STOP
0014 FE01 Z0_STOP
0018 FE01 Z1_STOP
001C FE01 X_TOTAL_0_RDBK
0020 FE01 X_TOTAL_1_RDBK
0024 FE01 0,1_DTA_PAT
0028 FE01 FIFO_0 WRT
002C FE01 FIFO_1 WRT
0030 FE01 TAG_DEF_1
0034 FE01 FE_DONE_0
0038 FE01 FE_DONE_1
003C FE01 Preload data counter 0-1
Hardware and Software Design • Manufacturing Services
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Front End Filter Channels 2,3
Decode number Address offset Chip Definition
1 0040 FE23 TAG_DEF_2
0044 FE23 X2_STOP
0048 FE23 X3_STOP
004C FE23 Y2_STOP
0050 FE23 Y3_STOP
0054 FE23 Z2_STOP
0058 FE23 Z3_STOP
005C FE23 X_TOTAL_2_RDBK
0060 FE23 X_TOTAL_3_RDBK
0064 FE23 2,3_DTA_PAT
0068 FE23 FIFO_2 WRT
006C FE23 FIFO_3 WRT
0070 FE23 TAG_DEF_3
0074 FE23 FE_DONE_2
0078 FE23 FE_DONE_3
007C FE23 Preload data counter 2-3
Hardware and Software Design • Manufacturing Services
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Address Generator Channels 0-3
Decode number Address offset Chip Definition
2 0080 ADD0_3 Start ADD CH 0
0084 ADD0_3 Start ADD CH 1
0088 ADD0_3 Start ADD CH 2
008C ADD0_3 Start ADD CH 3
0090 ADD0_3 Length CH 0
0094 ADD0_3 Length CH 1
0098 ADD0_3 Length CH 2
009C ADD0_3 Length CH 3
00A0 ADD0_3 CNTL CH 0
00A4 ADD0_3 CNTL CH 1
00A8 ADD0_3 CNTL CH 2
00AC ADD0_3 CNTL CH 3
00B0 ADD0_3 SDRAM Base 0-3
00B4-00B8 ADD0_3 Spare
00BC ADD0_3 Status 0-3
3 spare
Hardware and Software Design • Manufacturing Services
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Front End Filter Channels 4,5
Decode number Address offset Chip Definition
4 0100 FE45 TAG_DEF_4
0104 FE45 X4_STOP
0108 FE45 X5_STOP
010C FE45 Y4_STOP
0110 FE45 Y5_STOP
0114 FE45 Z4_STOP
0118 FE45 Z5_STOP
011C FE45 X_TOTAL_4_RDBK
0120 FE45 X_TOTAL_5_RDBK
0124 FE45 4,5_DTA_PAT
0128 FE45 FIFO_4 WRT
012C FE45 FIFO_5 WRT
0130 FE45 TAG_DEF_5
0134 FE45 FE_DONE_4
0138 FE45 FE_DONE_5
013C FE45 Preload data counter 4-5
Front End Filter Channels 6,7
Decode number Address offset Chip Definition
5 0140 FE67 TAG_DEF_6
0144 FE67 X6_STOP
0148 FE67 X7_STOP
014C FE67 Y6_STOP
0150 FE67 Y7_STOP
0154 FE67 Z6_STOP
0158 FE67 Z7_STOP
015C FE67 X_TOTAL_6_RDBK
0160 FE67 X_TOTAL_7_RDBK
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