Freescale Semiconductor MC68881 Manuale utente

General Description

Programming Model

Operand Data Formats

Instruction Set

Coprocessor Programming

Exception Processing

Coprocessor Interface

Instruction Executive Timing

Functional Signal Descriptions

Bus Operation

Interfacing Methods

Electrical Specifications

Ordering Information and Mechanical Data

Glossary

Abbreviations and Acronyms

Index

FLOATING

POINT

COPROCESSOR

USER'S

MANUAL

Second Edition

PRENTICE

HALL,

Englewood

Cliffs,

N.J.

07632

Freescale Semiconductor,

Inc.,

1989

reproduced, in any form or by any means,

without permission in writing from the publisher.

This document contains information on a new product. Specifications and

information herein are subject tochange without notice. Freescale reserves

the right to make changestoany products herein toimprove functioning or

design. Although the information in this document has been carefully re

viewedand is believed tobereliable, Freescale does not assume any liabiliy

arisingoutoftheapplication oruseofanyproductorcircuit described herein;

neither does it convey any license under its patent rights nor the rights of

other.

Freescale Semiconductor,Inc.generalpolicy doesnotrecommendtheuseofitscomponents

in life support applications where in a failure or malfunction of the component may directly

threaten lifeor injury. Per FreescaleTermsandConditions ofSale,theuserof IFreescalecomponents

in life support applications assumesall risk of such use and indemnifies Freescaleagainst

all damages.

Printed in the United States of America

I0987654321

ISBN

0-13-5b7009-B

Prentice

Hall International (UK) Limited, London

Prentice

Hall of Australia Pty. Limited, Sydney

Prentice

Hall Canada Inc., Toronto

Prentice

Hall Hispanoamericana, S.A., Mexico

Prentice

Hall of India Private Limited,

New

Delhi

Prentice

Hall of Japan, Inc., Tokyo

Simon

Schuster Asia Pte. Ltd., Singapore

Editora Prentice

Hall do Brasil, Ltda., Rio de Janeiro

TABLE OF CONTENTS

Paragraph Page

Number Title Number

1.1

1-2

1.2.1

1.2.2

1.3

1.3.1

1.3.2

1.3.3

1.3.4

1.4

1.4.1 •

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.5

1.6

Section 1

General Description

The Coprocessor Concept

...........................................................

1-2

Hardware Overview

...................................................................

1-3

Bus Interface Unit

.................................................................

1-6

Coprocessor Interface

...........................................................

1-9

Operand Data Formats ............................................................... 1-10

Integer Data Formats

.............................................................

1-11

Floating-Point Data Formats

...................................................

1-11

Packed Decimal String Real Data Format

..................................

1-11

Data Format Summary

.........................................................

1-12

Instruction Set

..........................................................................

1-12

Moves

...............................................................................

1-12

Move Multiple Registers ....................................................... 1-13

Monadic Operations ............................................................. 1-14

Dyadic Operations ............................................................... 1-14

Branch, Set, and Trap-On Condition ........................................ 1-15

Miscellaneous Instructions .................................................... 1-15

Addressing Modes .................................................................... 1-15

MC68882 Programming Considerations ................. ........................ 1-16

2.1

2.2

2.2.1

2.2.2

2.3

2.3.1

2.3.2

2.3.3

2.3.4

2.4

3.1

3.2

3.2.1

3.2.2

3.2.3

Section

Programming Model

Floating-Point Data Registers

.......................................................

2-1

Floating-Point Control Register .................................................... 2-2

FPCR

Exception

Enable Byte

...................................................

2-2

FPCR Mode Control Byte....................................................... 2-3

Floating-Point Status Register............. .

........................................

2-4

FPSR Floating-Point Condition Code Byte

.................................

2-4

FPSR Quotient Byte

.............................................................

2-6

FPSR Exception Status Byte

...................................................

2-6

FPSR Accrued Exception Byte

................................................

2-7

Floating-Point Instruction Address Register

.....................................

2-8

Section

Operand Data Formats

Integer Data Formats

............................................................ . ....

3-1

Binary Real Data Formats

...........................................................

3-2

Normalized Numbers

...........................................................

3-4

Denormalized Numbers

........................................................

3-4

Zeros................................................................................. 3-5

MC68881/MC68882 USER'S MANUAL FREESCALE

Paragraph

Number

3,2.4

3.2.5

3.2.6

3.3

3,4

3.5

3,5.1

3,5.2

3.6

4.1

4.2

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.3

4.3.1

4.3.2

4.3.3

4.4

4.4.1

4.4:2

4.4.3

4.5

4.5.1

4.5,2

4.5.3

4.5.4

4.5.4.1

4.5.4.2

4.5.5

4.5.5.1

4.5.5.2

4.6

4.7

4.7.1

4.7.1.1

4.7.1.2

4.7.1.3

4.7.1.4

4.7.1.5

4:7.1.6

4.7.1.7

TABLE OF CONTENTS (Continued)

Page

Title Number

Infinities ............................................................................ 3-5

Not-A-Numbers ................................................................... 3-5

Binary Real Data Summary

....................................................

3-6

Packed Decimal Real Data Format ................................................ 3-6

Internal Data Format.................................................................. 3~7

Format Conversions

..................................................................

3-8

Conversion to Extended Precision Data Format .......................... 3-8

Conversions to Other Data Formats ......................................... 3-9

Data Format Details................................................................... 3-9

Section

Instruction Set

Instruction Description Conventions.............................................. 4-1

Instruction Groups .................................................................... 4-1

Data Movement Operations ................................................... 4-2

Dyadic Operations ,.............................................................. 4-2

Monadic Operations............................................................. 4-3

Program Control Operations .................................................. 4-4

System Control Operations.................................................... 4-5

Computational Accuracy ............................................................. 4-5

Arithmetic Instructions ......................................................... 4-6

Transcendental Instructions ................................................... 4-7

Decimal Conversions............................................................ 4-8

Conditional Test Definitions ........................................................ 4-8

IEEE Nonaware Tests ........................................................... 4-10

IEEE Aware Tests ................................................................ 4-11

Miscellaneous Tests ............................................................. 4-12

Detailed Instruction Descriptions .................................................. 4-12

Addressing Modes............................................................... 4-12

Instruction Description Format

...............................................

4-13

Operation Tables...............

, .................................................

4-13

NANs

................................................................................

4-15

Nonsignaling NANs ........................................................ 4-15

Signaling NANs ............................................................. 4-15

Operation Post Processing..................................................... 4-15

Setting Floating-Point Condition Codes............................... 4-I6

Underflow, Round, Overflow ............................................ 4-16

Individual Instruction Descriptions ................................................ 4-17

Instruction Encoding Details ........................................................ 4-125

General Type Coprocessor Instruction Format ........................... 4-125

External Operand-to-Register Instructions............................ 4-127

Move Constant to Floating-Point Data Register Instructions..... 4-129

Move to External Destination Instructions ........................... 4-129

Move System Control Register Instructions ......................... 4-130

Move Multiple Floating-Point Data Registers Instructions ........ 4-131

Undefined, Reserved Command Words .............................. 4-133

FREESCALE

vi MC68881/MC68882 USER'S MANUAL

Paragraph

Number

4.7.2

4.7.3

4.7.4

4.7.5

4.8

4.8.1

4.8.2

4.8.3

4.8.4

4.8.5

4.8.6

4.9

5.1

5.1.1

5.1.1.1

5.1.1.2

5.1.2

5.1.2.1

5.1.2.2

5.1.2.3

5.1.2.4

5.2

5.2.1

5.2.2

5.2.3

5.2.3.1

5.2.3.2

5.2.3.3

5.2.3.4

5.2.3.5

5.2.3.6

5.2.4

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

TABLE OF CONTENTS (Continued)

Title Page

Number

FDBcc, FScc, and FTRAPcc Instruction Formats .........................

Conditional Branch Instruction Format ....................................

Save Instruction Format: ......................................................

Restore Instruction Format ...................................................

Instruction Format Summary .... ..................................................

Coprocessor ID Field ...........................................................

Effective Address Field ........................................................

4-133

4-135

4-137

4-138

Source Specifier Field

...........................................................

4-138

Destination Register Field...................................................... 4-139

Conditional Predicate Field ...................................................." 4-139

Instruction Format Diagrams ....................................................... 4-141

Section 5

CoprocessorProgramming

Applications Programming..................................... ..................... 5-1

Concurrency ......................................... .............................. 5-1

Concurrent Integer and Floating-Point Computations ............. 5-1

Concurrent Floating-Point Computations ............................. 5-2

Optimization of Code for the MC68882 ..................................... 5-9

Unrolling Loops ............................................................. 5-9

Avoiding Register Conflicts. ............................................. 5-9

Arranging FMOVE Instructions .......................................... 5-9

Performance Improvement Example .................................. 5-10

Systems Programming ............................................................... 5-10

State Frame Sizes

................................................................

5-10

Exception Handler Code... 5-11

Processing of Special Conditions

................................

............ 5-12

Interrupts ..................................................................... 5-13

Bus Arbitration .............................................................. 5-13

Context Switching .......................................................... 5-13

Bus Errors .................................................................... 5-14

Exception Processing ...................................................... 5-14

Simultaneous Floating-Point Exception and Task

Switch Interrupt .......................................................... 5-14

Detecting Coprocessor Presence ............................................. 5-15

Section

Exception Processing

Coprocessor-Detected Exceptions ................................................. 6-2

Branch/Set on Unordered (BSUN) ........................................... 6-5

Signaling Not-a-Number ........................................................ 6-6

Operand Error ...... ;..: .......................................................... 6-7

Overflow ........................................................................... 6-9

Underflow ......................................................................... 6-11

Divide by Zero .................................................................... 6-14

MC68881/MC68882 USER'S MANUAL

FREESCALE

vii

Paragraph

Number

6.1.7

6.1.8

6.1.9

6.1.10

6.1.11

6.1.12

6.1.13

6.2

6.2.1

6.2,2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.3

6.4

6.4.1

6.4.2

6.4.2.1

6.4.2.2

6.4.2.3

6.4.3

6.4.3.1

6.4.3.2

6.4.3.3

6.4.3.4

6.4.3.5

6.4.4

6.4.5

TABLE OF CONTENTS (Continued)

Page

Title

Number

Inexact Result ..................................................................... 6-15

Inexact Result on Decimal Input.............................................. 6-18

Multiple Exceptions ............................................................. 6-19

IEEE Exception and Trap Compatibility..................................... 6-19

Illegal Command Words

.......................................................

6-20

Coprocessor-Detected Protocol Violation .................................. 6-20

Recovery from Exceptions ..................................................... 6-22

Main Processor Detected Exceptions

.............................................

6-24

Trap on Coprocessor Condition Instruction ............................... 6-24

Illegal

Instructions ......... :..................................................... 6-24

Main-Processor-Detected Protocol Violations ............................. 6-25

Trace Exceptions ...................................... ........................... 6-25

• Interrupt ............................................................................ 6-26

Address and Bus Errors ................... :.................................... 6-27

Privilege Violations .............................................................. 6-27

Format Error Exceptions ....................................................... 6-28

MC68882 Exception Handlers ...................................................... 6-28

Context Switching ..................................................................... 6-28

FSAVE and FRESTORE Instruction Overviews ............................ 6-29

State Frames ...................................................................... 6-29

Null State Frame............................................................ 6-32

Idle State Frame ............................................................ 6-32

Busy State Frame........................................................... 6-35

FSAVE Protocol................................................................... 6-36

Reset Phase .................................................................. 6-37

Idle Phase .................................................................... 6-38

Initial Phase

..................................................................

6-38

Middle Phase ................................................................ 6-38

End Phase .................................................................... 6-38

FRESTORE Protocol ............................................................. 6-38

Context Switching Summary .................................................. 6-39

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

7.2.11

Section

Coprocessor Interface

Chip-Select Decode ................................................................... 7-1

Coprocessor Interface Registers ................................................... 7-2

Response CIR ($00) .............................................................. 7-3

Control CIR ($02) ................................................................. 7-4

Save CIR ($04) .................................................................... 7-5

Restore CIR ($06)

.................................................................

7-5

Operation Word CIR ($08) ..................................................... 7-5

Command ClR ($0A)............................................................. 7-5

Condition CIR ($0E) .............................................................. 7-6

Operand CIR ($10)

...............................................................

7-6

Instruction Address CIR ($18)

.................................................

7-7

Operand Address CIR ($1C) ................................................... 7-8

FREESCALE

viii

MC68881/MC68882 USER'S MANUAL

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

7.3

7.4

7.4.1

7.4.2

7.4.2.1

7.4.2.2

7.4.2.3

7.4.2.4

7.4.2.5

7.4.2.6

7.4.2.7

7.5

7.5.1

7.5.1.1

7.5.1.2

7.5.1.3

7.5.1.4

7.5.1.5

7.5.2

7.5.3

7.5.3.1

7.5.3.2

7.5.4

7.5.4.1

7.5.4.2

7.514.3

7.5.4.4

7.5.4.5

7.5.4.6

7.5.4.7

!nterprocessor Transfers ....... ,..................................................... 7-8

Coprocessor Instructions ............................................................ 7-8

Instruction Protocol.................................... .......................... 7-9

Response Primitives............................................................. 7-10

Null Primitive ................................................................ 7-11

Evaluate Effective Address and Transfer Data Primitive .......... 7-13

Transfer Single Main Processor Register Primitive ................ 7-14

Transfer Multiple Coprocessor Registers Primitive................. 7-15

Take Pre-lnstruction Exception Primitive ............................. 7-16

Take Mid-Instruction Exception Primitive............................. 7-18

Response Primitive Summary ........................................... 7-19

Instruction Dialogs .................................................................... 7-19

General Instructions ............................................................. 7-21

External-to-Register (OPCLASS 010) ................................... 7-22

Move Control Registers (OPCLASS 100 and 101) .................. 7-26

Move Multiple FPn (OPCLASS 110 and 111)......................... 7-27

Conditional Instructions ........................................................ 7-28

Context Switch Instructions ................................................... 7-28

FSAVE ......................................................................... 7-29

FRESTORE............................................... ..................... 7-30

Exception Processing ........................................................... 7-31

Take Pre-lnstruction Exception .......................................... 7-31

Take Mid-Instruction Exception ......................................... 7-32

Mid-Instruction Interrupt .................................................. 7-35

Take BSUN Exception ..................................................... 7-38

F-Line Emulator Exception ............................................... 7-39

Format Exception, FSAVE Instruction ................. ................ 7-39

Format Exception, FRESTORE Instruction .... ........................ 7-40

8.1

8.1.1

8.1.2

8.1.3

8.2

8.3

8.4

8.5

8.5.1

8.5.1.1

8.5.1.2

8.5.1.3

8.5,1.4

Section 8

Instruction Execution Timing

Factors Affecting Execution Times

................................................

8-1

Instruction Start-Up Phase......... ...........: .................. .............. 8-3

Calculation Phase ............................................... ;............... . 8-3

Round/Store Result Phase ............................... ...................... 8-4

Concurrent Instruction Execution

........................................... .

...... 8-4

Interrupt Latency Times........................................... ................... 8-5

Coprocessor Interface Overhead

...................................................

8-6

Execution Timing Tables ............................................................ 8-10

Timing Tables for Typical Execution

........................................

8-11

Effective Address Calculations .......................................... 8-12

Arithmetic Operations.. 8-12

MC68882 Concurrent Operations ....................................... 8-13

Move Control Register and FMOVEM Operations .................. 8-17

MC68881/MC68882 USER'S MANUAL FREESCALE

TABLE OF CONTENTS (Continued}

Paragraph Page

Number Title Number

8.5.1.5

8.5.1.6

8.5.2

8.5.2.1

8.5.2.2

8.5.2.3

8.5.2.4

8.5.2.5

8.5.2.6

8.5.2.7

8.5.2.8

8.5.2.9

8.5.2.10

8.6

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

9.12

9.13

9.14

10.1

10.1.1

10.1.2

10.1.3

10.2

10.3

10.4

10.4.1

10.4.2

10.4.3

10.5

10.6

Conditional Instructions................................................... 8-18

FSAVE and FRESTORE Instructions.................................... 8-18

MC68881 Detail Timing Tables ............................................... 8-19

Instruction Start-Up ........................................................ 8-25

Transfer Operand.............. ............................................. 8-26

Input Operand Conversion............................................... 8-27

Arithmetic Calculation..................................................... 8-27

Output Operand Conversion............................................. 8-33

Rounding and Exception Handling..................................... 8-33

Conditional Termination.................................................. 8-36

Multiple Register Transfer................................................ 8-37

State Frame Transfer ...................................................... 8-38

Exception Processing...................................................... 8-39

Main Processor Instruction Overlap Timing .................................... 8-40

Section

Functional Signal Descriptions

Address Bus (A0-A4) ................................................................. 9-1

Data Bus (D0-D31) .................................................................... 9-2

Size (SIZE)............................................................................... 9-2

Address Strobe (AS} .................................................................. 9-3

Chip Select (CS)........................................................................ 9-3

Read/Write (R/W) ...................................................................... 9-3

Data Strobe (DS) 9-3

Data Transfer and Size Acknowledge (DSACK0, DSACK1) .................. 9-3

Reset (RESET) .......................................................................... 9-4

Clock (CLK) .............................................................................. 9-4

Sense Device (SENSE) ............................................................... 9-5

Power (Vcc and GND) ............................................................... 9-5

No Connect (NC)....................................................................... 9-6

Signal Summary....................................................................... 9-6

Section 10

Bus Operation

Basic Transfer Mechanism Overview............................................. 10-1

32-Bit Port Size ................................................................... 10-2

16-Bit Port Size ................................................................... 10-3

8-Bit Port Size..................................................................... 10-4

Reset

Operation

........................................................................ 10-5

Chip Select Timing.................................................................... 10-6

Bus Cycle Functional Descriptions ................................................ 10-7

Synchronous Read Cycles ..................................................... 10-9

Asynchronous Read Cycles.................................................... 10-12

Asynchronous Write Cycles ................................................... 10-13

Inter-Cycle Timing Restrictions..................................................... 10-14

Coprocessor Interface Protocol Restrictions .................................... 10-15

FREESCALE

MC68881/MC68882 USER'S MANUAL

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