Freescale Semiconductor QorIQ T2080 Manuale utente

Freescale Semiconductor

Quick Start

1 Introduction

This document describes the T2080QDS board and its

related hardware kit. It also explains and verifies, the basic

board operations in a step-by-step format.

The document lists the settings required to connect switches,

connectors, jumpers, push buttons, and LEDs to the

peripheral devices.

The T2080QDS board functions with an integrated

development environment (IDE), such as Freescale

CodeWarrior. However, the instructions for working with the

IDE are beyond the scope of this document.

Document Number: T2080QDSQS

Rev. 0, 12/2015

Contents

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Related documentation . . . . . . . . . . . . . . . . . . . . . . . . 2

3. T2080 chassis images . . . . . . . . . . . . . . . . . . . . . . . . . 2

4. T2080QDS board drawings . . . . . . . . . . . . . . . . . . . . 4

5. Switch default settings . . . . . . . . . . . . . . . . . . . . . . . . 7

6. Connector default settings . . . . . . . . . . . . . . . . . . . . 16

7. Jumper default settings . . . . . . . . . . . . . . . . . . . . . . . 19

8. Push buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9. LED lights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10. Working environment . . . . . . . . . . . . . . . . . . . . . . . . 25

11. Getting started with T2080QDS . . . . . . . . . . . . . . . . 25

12. SerDes options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13. Appendix A: Combinations of SYSCLK and DDRCLK

14. Appendix B: Revision history . . . . . . . . . . . . . . . . . . 34

QorIQ T2080 Development System

Quick Start Guide

QorIQ T2080 Development System Quick Start Guide, Rev. 0

2Freescale Semiconductor

Related documentation

2 Related documentation

Table 1 lists the additional documents that you can refer to, for more information on T2080QDS.

Some of these documents may be available only under a non-disclosure agreement (NDA). To request

access to these documents, contact your local field applications engineer or sales representative.

NOTE

Freescale Semiconductor, Inc. does not own IR36021 Datasheet and

RTL8211EG-VB-CG Integrated 10/100/1000M Ethernet Transceiver

Datasheet and are mentioned solely for the reference purpose.

3 T2080 chassis images

This section demonstrates the manner in which the chassis are arranged on the T2080QDS board.

NOTE

The Hardware kit contents can be found in attached packing list provided

with the board support package.

Table 1. Related documentation

Document Description

T2080 QorIQ Integrated Multicore Communication Processor

Family Reference Manual

This document provides a detail description on T2080 QorIQ

multicore processor, and on some of its features like memory

map, serial interfaces, power supply, chip features, and clock

information.

T2080 QorIQ Advanced Multicore Processor Data Sheet This document contains T2080 information on pin

assignments, electrical characteristics, hardware design,

considerations, package information, and ordering

information.

IR36021 Datasheet This document details the Digital POL buck controller with I2C

and PMBus interface. IR36021 is used as dual power supply

(VDD & GVDD) for T2080 devices.

RTL8211EG-VB-CG Integrated 10/100/1000M Ethernet

Transceiver Datasheet

This document explains the use of RTL8211 as T2080 dual

channel GigaEthernet PHY.

T2080QDS Reference Manual This document details about the individual implementation of

T2080 Development System platform that supports T2080

Power Architecture processor.

QorIQ T2080 Development System Quick Start Guide, Rev. 0

Freescale Semiconductor 3

T2080 chassis images

Figure 1 and Figure 2 shows the T2080 QDS external view, that includes front and back enclosure of

chassis.

Figure 1. T2080QDS chassis front view

Figure 2. T2080QDS chassis back view

Figure 3 shows the open state of T2080QDS chassis:

QorIQ T2080 Development System Quick Start Guide, Rev. 0

4Freescale Semiconductor

T2080QDS board drawings

Figure 3. T2080QDS open state of chassis

4 T2080QDS board drawings

In this section:

•Section 4.1, “T2080QDS Component Side View”

•Section 4.2, “T2080QDS Print Side View”

QorIQ T2080 Development System Quick Start Guide, Rev. 0

Freescale Semiconductor 5

T2080QDS board drawings

4.1 T2080QDS Component Side View

Figure 4. T2080QDS Component Side View

QorIQ T2080 Development System Quick Start Guide, Rev. 0

6Freescale Semiconductor

T2080QDS board drawings

4.2 T2080QDS Print Side View

Figure 5. T2080QDS Print Side View

QorIQ T2080 Development System Quick Start Guide, Rev. 0

Freescale Semiconductor 7

Switch default settings

5 Switch default settings

Table 2 shows the default DIP-switch positions to establish the T2080QDS mode.

NOTE

Ensure the DIP-switches are set according to the default values.

Table 2. T2080QDS default configurations

Mode Term Default Value Unit

AVDD_CGA1,

AVDD_CGA2,

AVDD_PLAT,

AVDD_D1

PLL Supply Voltages

(Core, Platform, DDR, and SRDS)

1.8 V

AVDD_SRDS1,

AVDD_SRDS2,

SERDES PLL 1 & 2 Supply Voltages

(Filtered from XVDD)

1.35 V

G1VDD Voltage DDR DRAM I/O Supply Voltage 1.5[Default]/1.35 V

S1VDD, S2VDD Voltage Core power supply for SerDes transceiver 1.0 V

X1VDD, X2VDD Voltage Pad power supply for SerDes transceiver 1.35 V

OVDD Voltage General I/O Supply: MPIC, GPIO, eSDHC,

DDRCLK and IFC system control and power

management, clocking, debug, and JTAG I/O

voltage

1.8 V

DVDD Voltage DUART, I2C, DMA, 1.8[Default]/2.5/(3.3-Opti

onal)

CVDD Voltage eSPI & SDHC Blocks Supply 1.8[Default]/(2.5/3.3-Opti

onal)

LVDD Voltage Ethernet, EMI1, 1588, XFI 2.5 V

FA_VL Voltage Reserved for internal use 0/(1.025-Optional) V

PROG_MTR Reserved for internal use 0/(1.89-Optional) V

PROG_SFP Security fuse programming override supply 0/(1.89-Optional) V

TH_VDD Thermal monitor unit supply 1.8 V

VDD_LP Voltage Low Power Security Monitor Supply 1.0 V

VDD Cores & platform supply 1.025 V

USB_SVDD1 & 2 USB PHY Analog 1.0V Supply 1.025 V

USB_OVDD1 & 2 USB PHY Transceiver 1.8V Supply 1.8 V

USB_HVDD1 & 2 USB PHY Transceiver 3.3V Supply 3.3 V

SYSCLK (Synthesizer REF

CLK)

System Clock 100 MHz

Platform Clock Depends on RCW 600 MHz

DDR CLK (Synthesizer REF

CLK)

Depends on RCW 133.33 MHz

QorIQ T2080 Development System Quick Start Guide, Rev. 0

8Freescale Semiconductor

Switch default settings

D1_DDR_CLK Memory Bus Clock 933.333 MHz

Fman CLK Depends on RCW 700 MHz

Core Clock Depends on RCW 1800 MHz

SD1_REF1 CLK SerDes1 Reference Clock 1 156.250 MHz

SD1_REF2 CLK SerDes1 Reference Clock 2 100 MHz

SD2_REF1 CLK SerDes2 Reference Clock 1 100 MHz

SD2_REF2 CLK SerDes2 Reference Clock 2 100 MHz

EC1_GTXCLK_125 Eth1 MAC reference clock 125 MHz

EC2_GTXCLK_125 Eth2 MAC reference clock 125 MHz

USBCLK USB Block reference clock 24 MHz

TSEC_1588_CLK_IN PTP block input clock 125 MHz

RTC CLK Real-time Clock 3.125 MHz

Table 2. T2080QDS default configurations

Mode Term Default Value Unit

QorIQ T2080 Development System Quick Start Guide, Rev. 0

Freescale Semiconductor 9

Switch default settings

5.1 Switch configurations

Table 3 explains T2080QDS switch settings.

Table 3. Switch configurations

Configuration Details

SW1 Configuration SW1.1 – SW1.8: RCW_SRC[0:7]

(RCW Configuration Source)

Defines RCW configuration sources [0:8] as per T2080 RM

• 0_0001_0111 - 8bit NOR Flash (async 32b)

• 0_0010_0111 - 16b NOR Flash (Default)

• 0_0100_0000 - SDHC/eMMC

• 0_0100_0101 - SPI (24b addr.)

• 0_0100_1001 - I2C (ext. addr.)

• 0_100x_xxxx - Hard-coded RCW

• 1_0000_0100 - 8bit NAND Flash, 2kB page, 64pages/block

Note: Last configuration bit is defined by SW2.1

SW2 Configuration SW2.1 – RCW_SRC[8]

(RCW Configuration Source)

Defines RCW configuration sources [0:8] as per T2080 RM

SW2.[2:3] - GPIN [0:1]

11 - Application defined

SW2.[4:6] - ENGUSE [0:2]

111 - Reserved

SW2.7: RSP_DIS

• 1 - Reset Seq. normal [Default]

• 0 - Reset Seq. Pause

SW2.8: DRAM_TYPE

• 0 - DDR3 (1.5V) [Default]

• 1 - DDR3L (1.35V)

RCW_SRC7

RCW_SRC6

ON ’1’

RCW_SRC0

RCW_SRC1

RCW_SRC2

RCW_SRC3

RCW_SRC4

RCW_SRC5

DRAM_TYPE

RSP_DIS

ENGUSE2

ENGUSE1

ENGUSE0

GPIN1

GPIN0

ON ’1’

RCW_SRC8

QorIQ T2080 Development System Quick Start Guide, Rev. 0

10 Freescale Semiconductor

Switch default settings

SW3 Configuration SW3.[1:4]: SYSCLK Rate

• 0000 - 66.667 MHz

• 0001 - 83.333 MHz

• 0010 - 100.000 MHz (Default)

• 0011 - 125.000 MHz

• 0100 - 133.333 MHz

• 0101 - 150.000MHz

• 0110 - 160.000 MHz

• 0111 - 166.667MHz

• 1000 - 64.000 MHz

SW3.[5:6]: DDR Clock Rate

• 00 - 66.667 MHz

• 01 - 100.00 MHz

• 10 - 125.000 MHz

• 11 - 133.333 MHz [Default]

SW3.7: Spare

• 1 - [Default]

SW3.8: SERDES Spread Spectrum

• 0 - Disable CLK1, and CLK2 [Default]

• 1 - Enable CLK1, and CLK2

Note: For valid combinations of SYSCLK and DDRCLK, see

Section 13, “Appendix A: Combinations of SYSCLK and

DDRCLK”.

SW4 Configuration SW4.[1:2]: SERDES1 Clock1

• 00 - 100.00 MHz (from 8T49N222A)

• 01 - 125.000 MHz

• 10 - 156.250 MHz [Default]

• 11 - 100.00MHz

SW4.[3:4]: SERDES1 Clock2

• 00 - 100.00 MHz (from 8T49N222A)

• 01 - 125.000 MHz

• 10 - 156.250 MHz

• 11 - 100.00MHz [Default] (fixed from 871S1022EKLFT)

SW4.[5:6] SERDES2 Clock1

• 00 - 100.00 MHz (from 8T49N222A)

• 01 - 125.000 MHz

• 10 - 156.250 MHz

• 11 - 100.00MHz [Default] (fixed from 871S1022EKLFT)

SW4.[7:8] SERDES2 Clock2

• 00 - 100.00 MHz (from 8T49N222A)

• 01 - 125.000 MHz

• 10 - 156.250 MHz

• 11 - 100.00MHz [Default] (fixed from 871S1022EKLFT)

Table 3. Switch configurations

Configuration Details

SERDES_SS

SPARE

DDRCLK1

DDRCLK0

SYSCLK3

SYSCLK2

SYSCLK1

ON ’1’

SYSCLK0

SD2_SET3

SD2_SET2

SD2_SET1

SD2_SET0

SD1_SET3

SD1_SET2

SD1_SET1

ON ’1’

SD1_SET0

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