Fujitsu MB90890 Series Manuale utente
New Products
MB90890 Series
11
FIND Vol.21
No.12003
Product Description
The new series provides the world first high-performance
16-bit CPU integrating dual-operation flash memories,
together with a CAN controller, all within a LQFP-48
compact package.
CAN, Controller Area Network, is now the prevailing
global standard for LAN systems installed in automobiles.
The trend began in Europe, the first region in the world to
adopt the CAN controller-mounted microcontrollers, and
now FUJITSU is taking the lead in the industry by offering
diversified lineups of CAN microcontrollers as solutions for
the control of safety and amenity functions in automobiles.
The Company has just succeeded in offering the world first
microcontrollers mounted with flash memories that allow
simultaneous execution of read/write operations. With this
innovation, the flash memories applied conventionally for
readout purposes to change programs can now be used to
store various types of data during power interruptions.
This innovation offers several other advantages, as well. By
eliminating the need for EEPROM and related component
parts externally installed in the conventional designs, it
substantially reduces cost. It also facilitates the new application
of advanced controls for amenity, safety and communication,
including learning and tracing of maintenance data with the
use of large-density nonvolatile data memories.
The new series also offers an improved operating margin to
F2MC-16LX Family
16-bit Microcontroller
Mounted with Dual-Operation
Flash Memories
MB90890 Series
A new F2MC-16LX CPU-driven microcontroller series is available with 64 K-byte
dual-operation flash memories and a CAN controller integrated in a compact
48-pin package. This is the world first lineup of microcontrollers mounted with
dual-operation flash memories.
Photo 1 External View
New Products
MB90890 Series
12 FIND Vol.21 No.1 2003
pave the way towards packages that meet the higher
standards of safety and reliability listed below.
●An extended range of operating voltages between 3.5V and
5.5V, ensuring enhanced reliability for system operation
without possible voltage drops
●A 50% or greater increase in the margin for the circuit,
from the typical 0.3VCC to less than 0.5VCC. This enables
recognition of the 0 level of input voltages, opening up new
possibilities for the realization of noise-resistant systems
Product Features
■ Configured with FUJITSU,s original high-performance
F2MC-16LX CPU
■ Minimum instruction execution time of 62.5ns (at 16MHz
internal operation frequency)
■ System clock speed that can be increased by integral
multiples with the internal PLL clock (enables increased
internal operating frequency by an integral multiple of 1
to 4 times the base oscillator frequency)
■ Instruction set supporting C language and multitasking
■ Four available power-saving modes
●Sleep mode (CPU clock set OFF)
●Time-base timer mode
(All timers but the time-base timer set OFF)
●Stop mode (Base oscillator set OFF)
●CPU intermittent operation mode
(CPU operating clock repeatedly toggles ON and OFF based
on preset values)
■ Resources
●I/O port: A maximum of 36 ports available (including four
for higher-current outputs)
●18-bit time-base counter/Watchdog timer/Clock timer:1
channel
●8/16-bit PPG timer : 8-bit×4-channel, or 16-bit×2-channel
●16-bit reload timer: 2 channels
●16-bit I/O timer
16-bit free-running timer :1 channel
16-bit input capture (ICU) :4 channels
●UART:2 channels
●DTP/external interruption circuit : 4 channels
Dual-OperationFlashMemory
(UpperBank)
Dual-OperationFlashMemory
(LowerBank)
SA9：4K-byte
Write/eraseavailableinonebank
whileaprogramisexecutedinthe
otherbank
SA8：4K-byte
SA3：4K-byte
Dual-Operation
Read(Execution)
Write/Erase
Write/Erase
Read(Execution)
OR
CPU
SA2：4K-byte
SA1：4K-byte
SA0：4K-byte
SA7：4K-byte
SA6：4K-byte
SA5：16K-byte
SA4：16K-byte
Figure 1
Operation of Dual-Operation Flash Memory-Integrated Microcontroller Series MB90F897
Flash
Memory
RAM
CPU
①
①Rewritingfromflashmemory
toRAMProgramtransmission
ExistingFlashMemory
NoneedtotransferprogramstoRAM
whenflashmemoriesrewrite.
Dual-OperationFlashMemory
②Rewritingtoflashmemory
②
UpperBank
LowerBank
FlashMemory CPU
①
①Rewritingtoflashmemory
①
Figure 2 Operational Flow of CPU Rewrite by Flash Memory
New Products
MB90890 Series
13
FIND Vol.21
No.12003
●Delayed interruption generating module
●8/10-bit A/D converter: 8 channels
●Address match detection function
●Input level changeable by software
■ Package: FPT-48P-M26
Features of Dual-Operation
Flash Memory-Integrated
Microcontrollers
Fig. 1 outlines the operation of MB90F897 series
microcontrollers mounted with dual-operation flash
memories. While the upper bank flash memory handles
the execution of programs, the lower bank flash memory
can be applied for write/erase operations (or vice versa).
The new series also offers the following advantages for
system control.
■ No need to download programs to RAM when flash
memories self-rewrite to the CPU
Fig. 2 shows the operational flow for rewriting from flash
memories to the CPU.
In conventional microcontrollers mounted with flash
memories, programs have to be downloaded to RAM in
order to initiate rewrites, as these devices disallow rewrite
operations while programs are executed in the flash
memories. FUJITSU,s new microcontrollers integrated
with dual-operation flash memory allow rewrites by
executing programs on flash memory, thereby eliminating
the need to transfer the programs to RAM. This obviates the
need to make provisions against power failures during
program execution on RAM, and cuts down the program
download time as well.
■ Flash memory rewrites performed concurrently with
system control
Fig. 3 illustrates the control sequence for rewriting the
flash memory using interruption.
Conventionally, FUJITSU,s flash memory-integrated
microcontrollers have not been designed to allow
interruptions while the RAM is executing a program. After
the write/erase commands are issued, the software has to
check the flag to identify whether or not the write/erase
operation is completed. With the dual-operation flash
Enhancedsystemperformance Anyotherbankcanbereadout,evenwhiletheflashmemoryisbeingrewritten
Existingflashmemory
CPU
Previous
processing
Erase
Waitingtime
Nextprocessing
RAM
FlashMemory
CPU
Previous
processing
Nextprocessing
Erase
UpperBank
LowerBank
Dual-OperationFlashMemory
Eraseinstruction
Eraseinstruction
READ
instruction
READ
instruction
READ
instruction
READ
instruction
HigherSpeed
Figure 3 Control of Flash Memory Rewrite Based on Interruption
New Products
MB90890 Series
14 FIND Vol.21 No.1 2003
memory-integrated microcontrollers, the interruption can
take place in response to any interruption factor generated
after the write/erase is completed, thus enabling the
processing of other programs after the write/erase command is
issued. Write/erase operations for flash memories are smoothly
and reliably executed while system control is in progress.
Fig. 4 provides the specifications for bank-to-bank
transmission of the interruption vector.
The interruption vector is transmitted to the upper bank
flash memory to rewrite the flash memory in the lower
bank, and vice versa. Thus, interruption-based control is
available for rewriting in either bank.
■ The software sector-protect function prevents erroneous
writing /erasing of flash memory
In the new series, settable sector-protect bits are assigned
to protect individual sectors. An
0
setting in the bit sets
the sector-protect function active, thereby protecting the
target sector against attempts to perform write/erase
operations. Once
0
is set, the
1
setting (to enable the
write/erase) is disabled until any reset factor can be
generated. This ensures that the flash memories are fully
protected against write/erase attempts even in the case of
program runaway.
■ Dual-operation flash memory-integrated microcontroller
substitutes for an external EEPROM
Using the dual-operation flash memory-integrated
microcontroller as a substitution for EEPROM offers the
following benefits.
●Reduced system board mounting area
The mounting area equivalent to an EEPROM footprint
is reduced.
●Available EEPROM-like sector configuration
Eight small-density (4K-byte) sectors are available,
providing an easy-to-handle sector configuration for the
data-rewrite area (Fig. 4).
●Faster write speed
The targeted write time is 32μs/byte (typical), markedly
faster than that with EEPROM.
Availabletransmissionofinterruptionvectordomain
UpperBank
Interruptionvectordomain
AllowablealternativeuseforEEPROM
Rewriting
domain
LowerBank
SA9：4K-byte
SA8：4K-byte
SA3：4K-byte
SA2：4K-byte
SA1：4K-byte
SA0：4K-byte
SA7：4K-byte
SA6：4K-byte
SA5：16K-byte
SA4：16K-byte
SENbit＝0 Compatiblewithprogramupdates
Rewriting
domain
SA9：4K-byte
SA8：4K-byte
SA3：4K-byte
SA2：4K-byte
SA1：4K-byte
SA0：4K-byte
SA7：4K-byte
SA6：4K-byte
SA5：16K-byte
SA4：16K-byte
SENbit＝1
Interruptionvectordomain
Figure 4 Specifications for Bank-to-Bank Transmission of Interruption Vector
New Products
MB90890 Series
15
FIND Vol.21
No.12003
●Improved data reliability
Data can be written in the chip without external communication,
eliminating concerns about data garble due to fluctuations in
communications lines caused by external noise.
Table 1 provides a list of available packages in this series,
Fig. 5 is a block diagram, and Fig. 6 shows pin assignments.
Development Environment
The new series is supported by SOFTUNETM V3, a FUJITSU
integrated software development environment. The
SOFTUNE V3 application software is designed to simplify
programming tasks to meet the diversified needs of
program designers. The hardware is compatible with
MB2140 Series, an emulator for the F2MC Family that
permits real-time debugging.
Table 2 lists available development tools.
Typical Applications
The new series is a lineup of 16-bit commodity-grade
microcontrollers tailor-engineered for applications that
require high-speed real-time processing, data rewriting,
or data storage to nonvolatile memory while executing
programs on flash memories. Each device is incorporated
in a compact 48-pin package suitable for system board
installation within a limited mounting space. ✱
NOTES
*
S
OFTUNE
is a trademark of FUJITSU LIMITED.
CPU
F2MC−16LXcore
16-bitfree-runningtimer
Clockcontrolcircuit
Dual-OperationFlashMemory
Clocktimer
Time-basetimer
RAM
X0，X1
RSTX
X0A，X1A
SOT1
SCK1
SIN1
AVCC
AVSS
AN0toAN7
AVR
ADTG
Internaldatabus
Pre-scaler
UART1
Pre-scaler
8/10-bitA/Dconverter
(8-channel)
UART0
Inputcapture(4-channel) IN0toIN3
INT4toINT7
TIN0，TIN1
TOT0，TOT1
PPG0toPPG3
TX
RX
16-bitPPGtimer(2-channel)
16-bitreloadtimer(2-channel)
DTP/Externalinterruption
CAN
Figure 5 Block Diagram
New Products
16 FIND Vol.21 No.1 2003
MB90V495G MB90F897/S
EvaluationType
Item
Model
Flashmemorytype
NotinstalledROMdensity 64K-byte
6K-byteRAMdensity
CPUfunctions
Numberofinstructions：351
Maximuminstructionexecutiontime：62.5nsatanoperatingfrequencyof4MHz(4timesthebaseoscillatorfrequency)
Availableaddressingtypes：23
Allowableprogrampatching：2addresspointers
Maximumstoragespace：16M-byte
Power-saving(Standbymode) Sleepmode/Clockmode/Time-basetimermode/Stopmode/CPUintermittentmode
I/Oport General-purposeI/Oport(CMOSoutput)：34(36
＊
)Fourofthemintendedforhigher-currentoutputports
Time-basetimer 8-bitfree-runningcounter
Interruptioninterval：1.024ms,4.096ms,16.834ms,131.072ms(atanoscillationclockfrequencyof4MHz)
16-bitreloadtimer
Numberofchannels：2
Countclockinterval：0.25μs，0.5μs，2.0μs(Machineclockfrequency16MHz)
Availableexternaleventcounting
Clocktimer 15-bitfree-runningcounter
Interruptioninterval：31.25ms，62.5ms，12ms，250ms，500ms，1.0ms，2.0ms(at8.192kHzsubclock)
DTP/Externalinterruption
Numberofchannels：4
Riseedge/Falledgeactivatedinresponsetotheinputof"H"and"L"levels
AvailableexternalinterruptionorextendedintelligentI/Oservice(EI2OS)
10-bitA/Dconverter
Numberofchannels：8
Resolution：Either10-bitor8-bit
Conversiontime：6.125μs (atamachineclockfrequencyof16MHz,includingthesamplingtime)
UART（SCI）
Numberofchannels：2
Withfullduplexdoublebuffers
Transmissionavailableineitherstate,synchronousorasynchronoustoclock
AlsocanbeusedasserialI/O
Dedicatedbaudrategeneratorincorporated
8/16-bitPPGtimer
Numberofchannels：2-channel(Availableinthe8-bit×4-channelconfiguration)
PPGoperationavailableinboththe8-bit×4-channeland16-bit×2-channelconfigurations
Allowableoutputofpulsewaveformatanydesiredperiodanddutyfactor
Countclock：62.5nsto1μs (atamachineclockfrequencyof16MHz)
Watchdogtimer Resetoccurringinterval：3.58ms,14.33ms,57.23ms,458.75ms(atanoscillationclockfrequencyof4MHz)
16-bitI/Otimer 16-bitfree-runningtimer：1channel
Inputcapture：4channels
Delayedinterruptiongenerating
module Interruptiongeneratingmodulefortaskchanging
Usedwiththereal-timeOS
2K-byte
CMOSProcess
PGA256Package LQFP-48
4.5Vto5.5VOperatingvoltage 3.5Vto5.5V
＊34forMB90897：36forMB90F897
Table 1 Product Lineup
MB90890 Series
New Products
MB90890 Series
17
FIND Vol.21
No.12003
TOPVIEW
P17/PPG336
P16/PPG235
P15/PPG134
P14/PPG033
P13/IN332
P12/IN231
P11/IN130
P10/IN029
X128
X027
CP37/ADTG 26
VSS
＊MB90F897：X0A，X1A
MB90F897S：P35，P36
AVCC
AVR
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P20/TIN0 25
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
AVSS
X1A/P36＊
X0A/P35＊
P33
P32/SIN0
P31/SCK0
P30/SOT0
P44/RX
P43/TX
P42/SOT1
P41/SCK1
P40/SIN1
P21/TOT0
P22/TIN1
P23/TOT1
P24/INT4
P25/INT5
P26/INT6
P27/INT7
MD2
MD1
MD0
RST
VCC
1
2
3
4
5
6
7
8
9
10
11
12
Figure 6 Pin Assignments
Hardware
Mainunit
MB2141A
Software
SOFTUNEV3Workbench
SOFTUNEV3CCompiler
SOFTUNEV3Assembler
SOFTUNEV3CAnalyzer
SOFTUNEV3CChecker
Emulationpod
MB2145-507
Probecable
MB2132-466
Table 2 Development Tools
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