Fujitsu MB91F109 FR30 Manuale utente

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

FR30

32-Bit Microcontroller

MB91F109

Hardware Manual

CM71-10106-1E

FUJITSU LIMITED

FR30

32-Bit Microcontroller

MB91F109

Hardware Manual

PREFACE

■Objectives and Intended Reader

The MB91F109 has been developed as one of the "32-bit single-chip microcontroller FR30

series" products that use new RISC architecture CPUs as their cores. It has optimal

specifications for embedding applications that require high CPU processing power.

This manual explains the functions and operations of the MB91F109 for the engineers who

actually develop products using the MB91F109. Read this manual thoroughly. Refer to the

instruction manual for details on individual instructions.

■Trademarks

FR stands for FUJITSU RISC controller, a product of Fujitsu Limited.

Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.

■Organization of This Manual

This manual consists of 16 chapters and an appendix.

Chapter 1 Overview

Chapter 1 provides basic general information on the MB91F109, including its characteristics,

a block diagram, and function overview.

Chapter 2 CPU

Chapter 2 provides basic information on the FR series CPU core functions including the

architecture, specifications, and instructions.

Chapter 3 Clock Generator and Controller

Chapter 3 provides detailed information on the generation and control of the clock that

controls the MB91F109.

Chapter 4 Bus Interface

Chapter 4 explains the basic items of the external bus interface, register configuration and

functions, bus operations, bus timing, and provides bus operation program samples.

Chapter 5 I/O Ports

Chapter 5 provides an overview of I/O ports, explains the I/O port register configuration and

the conditions for using external terminals as I/O ports.

Chapter 6 External Interrupt/NMI Controller

Chapter 6 provides an overview of the external interrupt/NMI controller, explains the register

configuration and functions, and operations of the external interrupt/NMI controller.

Chapter 7 Delayed Interrupt Module

Chapter 7 provides an overview of the delayed interrupt module, explains the register

configuration and functions, and operations of the delayed interrupt module.

Chapter 8 Interrupt Controller

Chapter 8 provides an overview of the interrupt controller, explains the register configuration

and functions, and operations of the interrupt controller. The chapter also explains the hold

request cancel request function using examples.

Chapter 9 U-TIMER

Chapter 9 provides an overview of the U-TIMER, explains the register configuration and

functions, and operations of the U-TIMER.

Chapter 10 UART

Chapter 10 provides an overview of the UART, explains the register configuration and

functions, and operations of the UART.

Chapter 11 A/D Converter (Successive Approximation Type)

Chapter 11 provides an overview of the A/D converter, explains the register configuration

and functions, and operations of the A/D converter.

Chapter 12 16-bit Reload Timer

Chapter 12 provides an overview of the 16-bit reload timer, explains the register

configuration and functions, and operations of the 16-bit reload timer.

Chapter 13 Bit Search Module

Chapter 13 provides an overview of the bit search module, explains the register configuration

and functions, and operations and save/restore processing of the bit search module.

iii

Chapter 14 PWM Timer

Chapter 14 provides an overview of the PWM timer, explains the register configuration and

functions, and operations of the PWM timer.

Chapter 15 DMAC

Chapter 15 provides an overview of the DMAC, explains the register configuration and

functions, and operations of the DMAC.

Chapter 16 Flash Memory

Chapter 16 explains the flash memory functions and operations.

The chapter provides information on using the flash memory from the FR CPU.

For information on using the flash memory from the ROM writer, refer to the user’s guide for

the ROM writer.

Appendix

The appendix provides information on I/O maps, interrupt vectors, terminal states in each

CPU status, notes on using the little endian area, and a listing of instructions. It includes

details of these types of information that are not covered by the text that can be referenced

for programming.

1. The contents of this document are subject to change without notice. Customers are advised to consult

with FUJITSU sales representatives before ordering.

2. The information and circuit diagrams in this document are presented as examples of semiconductor

device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is

unable to assume responsibility for infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

3. The contents of this document may not be reproduced or copied without the permission of FUJITSU

LIMITED.

4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office

automation and other office equipments, industrial, communications, and measurement equipments,

personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special applications where failure or abnormal

operation may directly affect human lives or cause physical injury or property damage, or where

extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls,

sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to

consult with FUJITSU sales representatives before such use. The company will not be responsible for

damages arising from such use without prior approval.

5. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,

damage or loss from such failures by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions.

6. If any products described in this document represent goods or technologies subject to certain

restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior

authorization by Japanese government should be required for export of those products from Japan.

How to Read This Manual

■Description Format of this Manual

Major terms used in this manual are explained below:

Term Meaning

I-BUS 16-bit wide bus used for internal instructions. Since the FR series uses

an internal Harvard architecture, independent buses are used for

instructions and data. A bus converter is connected to the I-BUS.

D-BUS Internal 32-bit wide data bus. Internal resources are connected to the

D-BUS.

C-BUS Internal multiplex bus. The C-BUS is connected to the I-BUS and D-

BUS via a switch. An external interface module is connected to the C-

BUS. Data and instructions are multiplexed in the external data bus.

R-BUS Internal 16-bit wide data bus. The R-BUS is connected to the D-BUS

via an adapter. Various I/O ports, the clock generator, and interrupt

controller are connected to the R-BUS. Since the R-BUS is 16 bits

wide in which addresses and data are multiplexed, it takes twice as

much or more cycle time than usual for the CPU to access these

resources.

E-unit Operation executing unit

φSystem clock output from the clock generator to each internal resource

connected to the R-BUS. The system clock at the highest speed

shows the same cycle as source oscillation but is divided into 1, 1/2, 1/

4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) by PCK1 and PCK0 of the clock

generator GCR register.

θSystem clock or operation clock for the CPU and resources connected

to a bus other than the R-BUS. The system clock at the highest speed

shows the same cycle as source oscillation but is divided into 1, 1/2, 1/

4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) by CCK1 and CCK0 of the clock

generator GCR register.

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