GOWIN GW2A Series Guida rapida

GW2A/GW2AR series of FPGA Products Schematic Manual

UG206-1.1E

www.gowinsemi.com

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GW2A/GW2AR series of FPGA Products

Schematic Manual

Introduction

Users should follow a series of rules during circuit board design when

using the GW2A/GW2AR series of FPGA products. This manual describes

the characteristics and special features of GW2A/GW2AR series FPGA

products and provides a comprehensive checklist to guide design

processes. The main contents of this guide are as follows:

Power Supply

JTAG download

MSPI download

Clock pin

Difference pin

READY, RECONFIG_N, DONE

MODE

JTAGSEL_N

FASTRD_N

EXTR

Pin Multiplexing

Reference for the external crystal oscillator circuit

GW2AR Bank voltage

Supported configuration modes

Pin Distribution

Power Supply

1. Overview

Voltage types of the GW2A/GW2AR series of FPGA products include

core voltage (VCC), PLL voltage (VCCPLL), auxiliary voltage (VCCX) and Bank

voltage (VCCIO).

VCCX is an auxiliary power supply that is used to connect the internal

part of the chip, with a 2.5V or 3.3V power supply. If no VCCX exists, I/O,

OSC, and BSRAM circuits will be impacted and the chip will not be

functional.

2. Power Index

Users should ensure GOWINSEMI products are always used within

GW2A/GW2AR series of FPGA Products Schematic Manual

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recommended operating conditions and range. Data beyond the working

conditions and range are for reference only. GOWINSEMI does not

guarantee that all devices will operate as expected beyond the standard

operating conditions and range.

Table 1 lists the recommended working range for each power voltage.

Table 2 Recommended Working Range

Name

Description

Min.

Max.

VCC

Power voltage

0.95V

1.05V

VCCPLL

PLL Power

0.95V

1.05V

VCCO

I/O Bank Power

1.14V

3.465V

VCCX

Auxiliary Power

3.135V

3.465V

3. Total Power

For specific density, packages, and resource utilization, GPA tools can

be used to evaluate and analyze the power consumption.

4. Power-on time

Reference range of power-on time: 0.2 ms ~ 2 ms.

Note!

If the power-on time is more than 2ms, you need to ensure that the power-on in

sequence is VCC, and then VCCX/VCCIO;

If the power-on time is less than 0.2ms, it is recommended to increase the

capacitance to prolong the power-on time.

5. Power Filter

Each FPGA power input pin is connected to the ground with a 0.1uF

ceramic capacitor.

The input end of the VCC core voltage should primarily conduct the

noise processing. Specific reference is as shown in Figure 1:

Figure 1 Noise Processing of the Input End of the VCC Core Voltage

GW2A/GW2AR series of FPGA products isolate and filter the VCCPLL.

Specific reference is as shown in Figure 2:

V1P0

VCC

4.7uF

GW2A/GW2AR series of FPGA Products Schematic Manual

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Figure 2 Isolate and Filter the VCCPLL

FB is a magnetic bead, reference model mh2029-221Y, ceramic

capacitance 4.7uF, 100nF and 10nF. It offers an accuracy of more than

±10%.

JTAG Download

1. Overview

JTAG download is used for downloading the bitstream data into the

SRAM, on-chip flash or off-chip flash of the FPGA.

2. Signal Definition

Table 3 Signal Definition of JTAG Configuration Mode

Name

I/O

Description

TCK

Serial clock input in JTAG mode

TMS

I, internal weak

pull-up

Serial mode input in JTAG mode

TDI

I, internal weak

pull-up

Serial data input in JTAG mode

TDO

Serial data output in JTAG mode

3. JTAG Circuit Reference

Figure 3 JTAG Circuit Reference

Note!

The resistance accuracy is not less than 5%;

The power supply of the 6th pin in the JTAG socket can be adjusted to VCC1P2,

VCC1P5, VCC1P8 and VCC2P5 as required.

4.7uF

VCCPLL

100nF

V1P0

10nF

TDO

4.7K

R22

TMS

VCC3P3

R22

GND

JTAG

122

344

566

788

910 10

TDI

R22

TCK

R22

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MSPI Download

1. Overview

As a master device, the MSPI configuration mode reads the

configuration data automatically from the off-chip flash and sends it to the

FPGA SRAM.

2. Signal Definition

Table 4 Signal Definition for MSPI Configuration Mode

Name

I/O

Description

MCLK

Clock output in MSPI mode

MCS_N

MCS_N in MSPI mode, low-active

Data input in MSPI mode

Data output in MSPI mode

3. MSPI Circuit Reference

Figure 4 MSPI Circuit Reference

Note!

The serial flash chip model is for reference only. Alternatively, serial flash storage with the

same index can be used. The resistance accuracy is not less than 5%.

Clock Pin

1. Overview

The clock pins include GCLK global clock pins and PLL clock pins.

GCLK: The GCLK pins in the GW2A/GW2AR series of FPGA products

distribute in four quadrants. Each quadrant provides eight GCLK networks.

The optional clock resources of the GCLK can be pins or CRU. Selecting

the clock from the dedicated I/Os can result in better timing.

PLL: Frequency (multiply and division), phase, and duty cycle can be

adjusted by configuring the parameters.

2. Signal Definition

Table 5 Signal Definition for Clock Pin

Name

I/O

Description

GCLKT_[x]

I/O

Pins in global clock input, T(True), [x]: global clock

No.

GCLKC_[x]

I/O

Pins for Global clock input, C(Comp), [x]: global

4.7K

MCLK

VCC3P3

W25Q64

GND

4DI 5

CLK 6

HOLD 7

VCC 8

MCS_N

VCC3P3

100nF

R 4.7K

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Name

I/O

Description

clock No.

LPLL_T_fb/RPLL_T_fb

L/R PLL feedback the input pin, T(True)

LPLL_C_fb/RPLL_C_fb

L/R PLL feedback the input pin, C(Comp)

LPLL_T_in/RPLL_T_in

L/R PLL clock input pin, T(True)

LPLL_C_in/RPLL_C_in

L/R PLL clock input pin, C(Comp)

3. Clock Input Selection

If the external clock inputs as a PLL clock, the user is advised to input

from the PLL dedicated pin. And the PLL_T end is selected if the external

clock inputs from the single-end.

GCLK is the global clock and is directly connected to all resources in

the device. The GCLK_T end is advised if the GCLK inputs from the

single-end.

Difference Pin

1. Overview

Differential transmission is a form of signal transmission technology

that operates according to differences between the signal line and the

ground line. The differential transmit signals on these two lines, the

amplitude of the two signals are equal and have the same phase but

demonstrate opposite polarity.

2. LVDS

LVDS is a low-voltage differential signal that offers low power

consumption, low bit error rate, low crosstalk, and low radiation. It

facilitates the transmission of data using a low-voltage swing high-speed

differential. Different packages employ different signals. Please refer to the

True LVDS section of the Package Pinout Manual for further details.

Note！

All BANKs in the GW2A/GW2AR series of FPGA products support True LVDS output;

BANK0/1 in the GW2A/GW2AR series of FPGAproducts support 100 ohm differential

input resistance;

If the BANK is used as the differential input, 100-ohm terminal resistance is needed；

The different line impedance of PCB is controlled at about 100 ohms.

READY, RECONFIG_N, DONE

1. Overview

RECONFIG_N is a reset function within the FPGA programming

configuration. FPGA can't configure if RECONFIG_N is low.

As a configuration pin, a low level signal with pulse width no less than

25ns is required to start GowinCONFIG to reload bitstream data according

to the MODE setting value. You can control the pin via the write logic and

trigger the device to reconfigure.

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READY, the FPGA can configure only when the READY signal is high.

The device should be restored by using the power on or triggering

RECONFIG_N when the READY signal is low.

As an output configuration pin, FPGA can be indicated for the current

configuration state. If the device meets the configuration condition, READY

signal is high. If the device fails to configure, the READY signal changes to

low. As an input configuration pin, you can reduce the READY signal via its

own logic or manually operate outside the device to delay configuration.

DONE, the DONE signal indicates that the FPGA is configured

successfully. The signal is high after successful configuration.

As an output configuration pin, FPGA can be indicated whether the

current configuration is successful. If configured successfully, DONE is

high, and the device enters into a working state. If the device failed to

configure, the DONE signal remains low. For the input type, the user can

reduce the READY signal via its own internal logic or manually operate

outside the device to delay progression to user mode.

When the RECONFIG_N or READY signals is low. The DONE signal

is low. DONE has no influence when SRAM is configuried through the

JTAG circuit.

2. Signal Definition

Table 6 Signal Definition

Name

I/O

Description

RECONFIG_N

I, internal weak

pull-up

Low-level pulse: Start new GowinCONFIG

configuration

READY

I/O

High-level pulse: The device can currently

be programmed and configured;

Low-level pulse: The device cannot be

programmed and configured,

DONE

I/O

High-level pulse: The device has been

successfully programmed and configured;

Low-level pulse: The configuration is

incomplete or has failed.

GW2A/GW2AR series of FPGA Products Schematic Manual

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3. Reference Circuit

Figure 5 Reference Circuit

Note!

The upper pull power supply is the bank voltage value of the corresponding pin;

The resistance accuracy is not less than ±5%.

MODE

1. Overview

MODE spans the MODE0, MODE1, MODE2, and GowinCONFIG

configuration MODE modes. When the FPGA powers on or a low pulse

triggers the RECONFIG_N mode, the device enters the corresponding

GowinCONFIG state according to the MODE value. As the number of pins

for each package is different, some MODE pins are not all packaged, and

the unpacked MODE pins are grounded inside. Please refer to the

corresponding PINOUT manual for further details.

2. Signal Definition

Table 7 Signal Definition

Name

I/O

Description

MODE2

I, internal weak

pull-up

GowinCONFIG modes selection pin.

MODE1

I, internal weak

pull-up

GowinCONFIG modes selection pin.

MODE0

I, internal weak

pull-up

GowinCONFIG modes selection pin.

4.7K

DONE

VCCO3

4.7K

RECONFIG_N

READY

4.7K

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3. Mode Selection

Table 8 Mode Selection

Configuration

MODE[2:0]

Instructions

JTAG

XXX

The GW2A(R) series of FPGAproducts

are configured by the external Host via a

JTAG interface.

GowinCONFIG

MSPI

000

As a master, the GW2A/GW2AR series

of FPGA products are configured by

reading data from an external flash (or

alternative device) through an SPI

interface3..

SSPI

001

The GW2A(R) series of FPGAproducts

are configured from an external Host via

a SPI interface.

SERIAL

101

The GW2A(R) series of FPGAproducts

are configured by the external Host via a

DIN interface.

CPU

111

The GW2A(R) series of FPGAproducts

are configured by the external Host via a

DBUS interface.

JTAGSEL_N

1. Overview

Select the signal in JTAG mode. If the JTAG pin is set as GPIO in

Gowin software, the JTAG pin is changed to GPIO pin after being powered

on and successfully configured. The JTAG pin can be recovered by

reducing the JTAGSEL_N. The JTAG configuration functions are always

available if no JTAG pin multiplexing is set.

2. Signal Definition

Table 9 Signal Definition

Pin Name

I/O

Description

JTAGSEL_N

I, internal weak

pull-up

Restore JTAG pin from GPIO to

configuration pin. Low level is valid

Note!

As GPIO, the JTAGSEL_N pin and the four pins (TCK, TMS, TDI, and TDO) configured

with JTAG are mutual exclusive;

If JTAGSEL_N is set to GPIO, the JTAG pin can only be used as a configuration pin;

If JTAG is set to GPIO, the JTAGSEL_N pin can only be used as a configuration pin.

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FASTRD_N

1. Overview

In MSPI configuration mode, signals are selected via reading the SPI

flash speed rate. FASTRD_N is normal read mode if high level; FASTRD_N

is high speed read mode if low level. Each manufacturer's flash high speed

read instruction is different. Please refer to the corresponding flash data

manual.

2. Signal Definition

Table 10 Signal Definition

Pin Name

I/O

Description

FASTRD_N

READY signal rising edge sampling

High: Normal flash access mode

Low: High-speed flash access mode

Note!

In the high-speed flash access mode: the clock frequency is greater than 30MHz.

EXTR

EXTR is a dedicated pin that needs to be connected to the ground with

10K resistance. The resistance precision is 1%.

Specific reference is as shown in:

GW2A/GW2AR series of FPGA Products Schematic Manual

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Figure 6 EXTR Pin Configuration

The resistance accuracy is ±1%.

Pin Multiplexing

1. Overview

Configure pin multiplexing refers to configuring during power-on, which

is used as a normal I/O after downloading the bitstream file.

Configure pin multiplex via the Gowin software:

a). Open the corresponding project in Gowin software;

b). Select “Project > Configuration > Dual Purpose Pin” from the menu

options, as shown in Figure 7;

c). Check the corresponding option to set the pin multiplex.

Figure 8 Pin Multiplex

2. Pin Multiplexing

SSPI: As a GPIO, SSPI can be used as input or output type;

MSPI: As a GPIO, MSPI can be used as input or output type;

RECONFIG_N GPIO can only be used as an output type. For

smooth configuration, set the initial value of RECONFIG_N as high

when multiplexing it.

10K

EXTR

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