IDT CPS-16 Manuale utente

July 10, 2012

IDTCPS-16/12/8

Central Packet Switch

User Manual

Revision 1.5

Tit

GENERAL DISCLAIMER

Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or perfor-

mance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein

does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata

which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as “reserved”

or “undefined” are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items. IDT products

have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application

carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied

upon for developing applications. Any use of such code examples shall be at the user's sole risk.

The IDT logo is registered to Integrated Device Technology, Inc. IDT and CPS are trademarks of Integrated Device Technology, Inc.

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual iii July 10, 2012

1 Device Overview.......................................................................................................................1-1

1.1 Device Description .......................................................................................................1-1

1.2 Key Features................................................................................................................1-2

1.3 Additional Resources ...................................................................................................1-2

1.4 Block Diagram..............................................................................................................1-3

1.5 Application Example: The Wireless Basestation..........................................................1-4

1.6 Functional Overview ....................................................................................................1-5

1.7 Functional Differences with PPS-Gen2 (80KSW0001) ................................................1-5

2 sRIO Ports ................................................................................................................................2-1

2.1 sRIO Port Definition .....................................................................................................2-1

2.2 Trace Function .............................................................................................................2-3

2.3 Packet Filtering ............................................................................................................2-7

2.4 Software Assisted Error Recovery ...............................................................................2-7

3 Switch Description ....................................................................................................................3-1

3.1 Conceptual Functionality..............................................................................................3-1

3.2 Switching Block and Elements.....................................................................................3-1

3.3 Switch Description .......................................................................................................3-2

3.4 Switching Scheduler and Priorities ..............................................................................3-3

3.5 Flow Control and Congestion Management.................................................................3-5

4 I2C Interface .............................................................................................................................4-1

4.1 Overview ......................................................................................................................4-1

4.2 Master/Slave Configuration..........................................................................................4-1

4.3 Temporary Master Mode ..............................................................................................4-1

4.4 Slave Mode ..................................................................................................................4-7

5 Error Management....................................................................................................................5-1

5.1 Error Management Functional Architecture ................................................................5-1

6 JTAG & Boundary Scan............................................................................................................6-1

6.1 JTAG and AC Extest Compliance ................................................................................6-1

6.2 Test Instructions ...........................................................................................................6-1

6.3 Device ID Register.......................................................................................................6-2

6.4 Initialization and Reset.................................................................................................6-2

6.5 Configuration Register Access.....................................................................................6-2

6.6 Boundary Scan ............................................................................................................6-3

7 Reference Clock .......................................................................................................................7-1

7.1 Reference Clock Specification .....................................................................................7-1

7.2 PLL...............................................................................................................................7-1

8 Programming the Device ..........................................................................................................8-1

8.1 Device Access .............................................................................................................8-1

8.2 Route Tables ................................................................................................................8-3

8.3 Device Programming ...................................................................................................8-9

8.4 Example of Programming ..........................................................................................8-12

8.5 Optional API Calls......................................................................................................8-13

Contents

IDT Table of Contents

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual iv July 10, 2012

9 Reset & Initialization.................................................................................................................9-1

9.1 Registers......................................................................................................................9-1

9.2 Initialization Steps........................................................................................................9-2

9.3 Initialization of RIO Ports .............................................................................................9-2

9.4 RIO System Bring Up...................................................................................................9-2

9.5 Serdes Initialization......................................................................................................9-2

10 Registers ...............................................................................................................................10-1

10.1 RapidIO Compliance..................................................................................................10-1

10.2 Register Type Field Definitions ..................................................................................10-1

10.3 Address Map..............................................................................................................10-2

10.4 Rapid IO Registers.....................................................................................................10-8

10.5 RIO extended feature registeR ................................................................................10-19

10.6 IDT Specific sRIO Extended Feature Set ................................................................10-24

10.7 Routing Table Registers...........................................................................................10-25

10.8 Trace Registers........................................................................................................10-26

10.9 Global Configuration Registers................................................................................10-31

10.10 Multicast Registers...................................................................................................10-38

10.11 Switching Port Registers..........................................................................................10-40

10.12 Error Registers.........................................................................................................10-47

10.13 QUAD Control Registers..........................................................................................10-52

11 References ............................................................................................................................ 11-1

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual v July 10, 2012

Figure 1.1 Block Diagram ..................................................................................................................1-3

Figure 1.2 CPS Interconnect..............................................................................................................1-4

Figure 1.3 Application Overview ........................................................................................................1-4

Figure 2.1 Trace Matching Criteria ....................................................................................................2-4

Figure 2.2 Illustration of the Trace Function within a Given Port .......................................................2-5

Figure 3.1 CPS Switch Core Block Diagram......................................................................................3-1

Figure 3.2 Input Buffer Diagram.........................................................................................................3-2

Figure 4.1 Bit Transfer on the I2C Bus ..............................................................................................4-8

Figure 4.2 START and STOP Signaling ............................................................................................4-8

Figure 4.3 Data Transfer....................................................................................................................4-9

Figure 4.4 Acknowledgment ..............................................................................................................4-9

Figure 4.5 Master Addressing a Slave with a 7-bit Address (Transfer Direction is Not Changed) ....4-9

Figure 4.6 Master Reads a Slave Immediately After the First Byte ...................................................4-9

Figure 4.7 Combined Format...........................................................................................................4-10

Figure 4.8 Master Addresses a Slave-Receiver with 10-bit Address...............................................4-10

Figure 4.9 Master Addresses a Slave Transmitter with 10-bit Address ...........................................4-10

Figure 4.10 Combined Format: Master Addresses a Slave with 10-bit Address ...............................4-10

Figure 4.11 Combined Format: Master Transmits Data to Two Slaves, Both with 10-bit Address ....4-11

Figure 4.12 Write Protocol with 10-bit Slave Address (ADS is 1) ......................................................4-12

Figure 4.13 Read Protocol with 10-bit Slave Address (ADS is 1)......................................................4-12

Figure 4.14 Write Protocol with 7-bit Slave Address (ADS is 0) ........................................................4-12

Figure 4.15 Read Protocol with 7-bit Slave Address (ADS is 0)........................................................4-13

Figure 5.1 Functional View of Error Management Block....................................................................5-1

Figure 6.1 JTAG Write Access...........................................................................................................6-3

Figure 6.2 JTAG Read Access ..........................................................................................................6-3

Figure 7.1 Reference Clock Representative Circuit...........................................................................7-1

Figure 7.2 Internal PLL Clock Generator ...........................................................................................7-2

Figure 8.1 Route Table Lookup Diagram...........................................................................................8-3

Figures

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual vi July 10, 2012

Table 2.1 Port Numbering.................................................................................................................. 2-1

Table 2.2 Port Configuration Examples............................................................................................. 2-2

Table 4.1 EEPROM Register Address Map....................................................................................... 4-3

Table 4.2 Register Map Example ...................................................................................................... 4-5

Table 4.3 EEPROM Format Example................................................................................................ 4-6

Table 4.4 I2C Address Pins............................................................................................................... 4-7

Table 5.1 Error Sources and Codes .................................................................................................. 5-1

Table 5.2 I2C Errors and Codes -- Group Number 0x1..................................................................... 5-2

Table 5.3 JTAG Errors and Codes -- Group Number 0x2.................................................................. 5-3

Table 5.4 Maintenance Handler Errors and Codes -- Group Number 0x3 ........................................ 5-4

Table 5.5 Configuration Errors and Codes -- Group Number 0x5 ..................................................... 5-5

Table 5.6 RIO SERDES Errors and Codes -- Group Number 0x6 .................................................... 5-6

Table 5.7 RIO Link Layer Errors and Codes -- Group Number 0x7................................................... 5-6

Table 5.8 RIO Link Protocol Errors and Codes -- Group Number 0x8 .............................................. 5-7

Table 5.9 RIO Logical and Transport Errors and Codes -- Group Number 0x9................................. 5-8

Table 5.10 Port Write Payload Definition............................................................................................5-11

Table 5.11 Maintenance Packet Format.............................................................................................5-11

Table 6.1 Test Instructions................................................................................................................. 6-1

Table 6.2 Configuration Registers ..................................................................................................... 6-2

Table 8.1 RIO Defined Maintenance Packet with CPS as Destination.............................................. 8-1

Table 8.2 RIO Defined Maintenance Response Packet generated by CPS...................................... 8-2

Table 8.3 Port Configuration.............................................................................................................. 8-4

Table 8.4 Multicast Mask Register References for Multicast Mask Port CSR Usage........................ 8-6

Table 8.5 Region Select .................................................................................................................... 8-7

Table 8.6 Port Number References................................................................................................... 8-7

Table 8.7 Multicast Mask References................................................................................................ 8-8

Table 9.1 Port Configuration at Power Up.........................................................................................9-1

Table 9.2 Default Speed Settings with SPD0 and SPD1................................................................... 9-2

Table 10.1 Register Types................................................................................................................. 10-1

Table 10.2 CPS Memory Map ........................................................................................................... 10-2

Table 10.3 DEV_IDENT_CAR 0x000000 .......................................................................................... 10-8

Table 10.4 DEV_INF_CAR 0x000004 ............................................................................................... 10-8

Table 10.5 ASSY_IDENT_CAR 0x000008........................................................................................ 10-9

Table 10.6 ASSY_INF_CAR 0x00000C ............................................................................................ 10-9

Table 10.7 PROC_ELEM_FEAT_CAR 0x000010 ........................................................................... 10-10

Table 10.8 SWITCH_PORT_INF_CAR 0x000014 ...........................................................................10-11

Table 10.9 SRC_OPS_CAR 0x000018 ........................................................................................... 10-12

Table 10.10 SW_MCAST_SUP_CAR 0x000030............................................................................... 10-13

Table 10.11 SW_RTE_TBL_LIM_CAR 0x000034............................................................................. 10-14

Table 10.12 SW_MULT_INF_CAR 0x000038 ................................................................................... 10-14

Table 10.13 HOST_BASE_DEV_ID_LOCK_CSR 0x000068 ............................................................ 10-14

Table 10.14 COMPONENT_TAG_CSR 0x00006C ........................................................................... 10-15

Table 10.15 STD_RTE_CONF_DESTID_SEL_CSR 0x000070........................................................ 10-15

Table 10.16 STD_RTE_CONF_PORT_SEL_CSR 0x000074 ........................................................... 10-16

Table 10.17 STD_RTE_DEFAULT_PORT 0x000078........................................................................ 10-16

Table 10.18 MCAST_MASK_PORT 0x000080 ................................................................................. 10-17

Table 10.19 MCAST_ASSOC_SEL_CSR 0x000084 ........................................................................ 10-17

Table 10.20 MCAST_ASSOC_OP_CSR 0x000088 .......................................................................... 10-18

Table 10.21 PORT_MAINT_BLOCK_HEAD 0x000100..................................................................... 10-18

Tables

IDT List of Tables

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual vii July 10, 2012

Table 10.22 PORT_LINK_TO_CTRL_CSR 0x000120...................................................................... 10-18

Table 10.23 PORT_GEN_CTRL_CSR 0x00013C............................................................................. 10-19

Table 10.24 RIO Extended Register Map.......................................................................................... 10-19

Table 10.25 PORT_0_LINK_MAINT_REQ_CSR 0x000140 ............................................................. 10-20

Table 10.26 PORT_0_LINK_MAINT_RESP_CSR 0x000144 ........................................................... 10-20

Table 10.27 PORT_0_LOCAL_ACKID_CSR 0x000148.................................................................... 10-21

Table 10.28 PORT_0_ERR_STAT_CSR 0x000158 .......................................................................... 10-22

Table 10.29 PORT_0_CTRL_CSR 0x00015C .................................................................................. 10-22

Table 10.30 LOCAL_RTE_CONF_DESTID_SEL_CSR 0x010070 ................................................... 10-24

Table 10.31 Routing Table Register .................................................................................................. 10-25

Table 10.32 Route Table Register 0xE00000-0xE1F7FC.................................................................. 10-25

Table 10.33 Trace Register Map ....................................................................................................... 10-26

Table 10.34 Port_0_Trace_Value_1_Block_0 0xE40000 .................................................................. 10-27

Table 10.35 Port_0_Trace_Value_1_Block_1 0xE40004 .................................................................. 10-27

Table 10.37 Port_0_Trace_Value_1_Block_3 0xE4000C.................................................................. 10-28

Table 10.36 Port_0_Trace_Value_1_Block_2 0xE40008 .................................................................. 10-28

Table 10.39 Port_0_Mask_Value_1_Block_0 0xE40014................................................................... 10-29

Table 10.38 Port_0_Trace_Value_1_Block_4 0xE40010 .................................................................. 10-29

Table 10.41 Port_0_MASK_Value_1_Block_2 0xE4001C ................................................................ 10-30

Table 10.42 Port_0_Mask_Value_1_Block_3 0xE40020................................................................... 10-30

Table 10.40 Port_0_MASK_Value_1_Block_1 0xE40018................................................................. 10-30

Table 10.44 CPS_CONTROL 0xF2000C .......................................................................................... 10-31

Table 10.43 Port_0_Mask_Value_1_Block_4 0xE40024................................................................... 10-31

Table 10.45 CONF_MOD_ERR_REPORT_ENABLE 0xF20014 ...................................................... 10-32

Table 10.46 AUXPORT_ERR_REPORT_ENABLE 0xF20018.......................................................... 10-33

Table 10.47 MAINT_ERR_REPORT_ENABLE 0xF2001C ............................................................... 10-33

Table 10.48 RIO_DOMAIN 0xF20020............................................................................................... 10-33

Table 10.49 RIO_PORT_WRITE_INFO 0xF20024 ........................................................................... 10-34

Table 10.50 RIO_PORT_WRITE_SRCID 0xF20028......................................................................... 10-34

Table 10.51 RIO_ASSY_IDENT_CAR 0xF2002C............................................................................. 10-35

Table 10.52 RIO_ASSY_INF_CAR 0xF20030 .................................................................................. 10-35

Table 10.53 PPS_SOFT_RESET 0xF20040..................................................................................... 10-35

Table 10.54 I2C_MASTER_CTRL 0xF20050.................................................................................... 10-36

Table 10.55 I2C_MASTER_STAT_CTRL 0xF20054 ......................................................................... 10-37

Table 10.56 MULTICAST Register Map ............................................................................................ 10-38

Table 10.57 MULTICAST0 0xF30000................................................................................................ 10-39

Table 10.58 Switching Port Register Map ......................................................................................... 10-40

Table 10.59 PORT_0_BUF_SIZE 0xF40000..................................................................................... 10-41

Table 10.60 PORT_0_OPS 0xF40004 .............................................................................................. 10-41

Table 10.61 PORT_0_ERR_REPORT_ENABLE 0xF40008............................................................. 10-43

Table 10.62 PORT_0_SWITCH_BUF_STATUS 0xF4000C .............................................................. 10-44

Table 10.63 PORT_0_ACK_CNTR 0xF40010 .................................................................................. 10-44

Table 10.64 PORT_0_NACK_CNTR 0xF40014................................................................................ 10-45

Table 10.65 PORT_0_SW_PKT_CNTR 0xF4001C .......................................................................... 10-45

Table 10.66 PORT_0_TRACE_MATCH_CNTR_1 0xF40020........................................................... 10-45

Table 10.67 PORT_0_TRACE_MATCH_CNTR_2 0xF40024........................................................... 10-45

Table 10.68 PORT_0_TRACE_MATCH_CNTR_3 0xF40028........................................................... 10-46

Table 10.69 PORT_0_TRACE_MATCH_CNTR_4 0xF4002C .......................................................... 10-46

Table 10.70 PORT_0_FILTER_MATCH_CNTR_1 0xF40030 ........................................................... 10-46

Table 10.71 PORT_0_FILTER_MATCH_CNTR_2 0xF40034 ........................................................... 10-46

Table 10.72 PORT_0_FILTER_MATCH_CNTR_3 0xF40038 ........................................................... 10-47

Table 10.73 PORT_0_FILTER_MATCH_CNTR_4 0xF4003C........................................................... 10-47

Table 10.74 ERR_CAP_REG 0xFD0000 .......................................................................................... 10-47

Table 10.75 ERR_LOG_RD 0xFD0004............................................................................................. 10-48

Table 10.76 SPECIAL_ERR Register Map........................................................................................ 10-48

IDT List of Tables

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual viii July 10, 2012

Table 10.77 SPECIAL_ERR_0 0xFD0008 ........................................................................................ 10-48

Table 10.78 ERR_FLAG 0xFD0028 .................................................................................................. 10-50

Table 10.79 ERR_COUNTER 0xFD002C ......................................................................................... 10-50

Table 10.80 ERR_RESET 0xFD0030................................................................................................ 10-51

Table 10.81 QUAD_CTRL Control Register Map.............................................................................. 10-52

Table 10.82 QUAD_0_CTRL 0xFF0000............................................................................................ 10-52

Table 10.83 QUAD_0_ERR_REPORT_EN 0xFF0004...................................................................... 10-54

Table 10.84 QUAD_CTRL_BROADCAST 0xFFF000 ....................................................................... 10-54

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual ix July 10, 2012

Introduction

This user reference manual includes hardware and software information for the CPS family products. It

applies to CPS-16, CPS-12, and CPS-8. The only deference is port number, device ID and register map file.

The pinout is covered in each individual datasheet. All the description through out the user manual is

default as CPS-16. The register file of CPS-12 and CPS-8 is a subset of CPS-16, the registers associated

with invalid port/quad are treated as reserved.

DEVICE ID: CPS-16 device ID is 0x35B, CPS-12 device ID is 0x35D, CPS-8 device ID is 0x35C.

PORT/QUAD NUMBER: CPS-16 has 4 QUAD provides up to 16 ports. CPS-12 has 3 QUAD pro-

vides up to 12 ports. CPS-8 has 2 QUAD provides up to 8 ports.

Content Summary

Chapter 1, “CPS Device Overview,” provides a complete introduction to the capabilities of the CPS. It

includes the major difference from PPS device.

Chapter 2, “Serial RapidIO Ports,” covers the device’s Serial RapidIO ports. These ports are RapidIO

specification 1.3 compliant. Also covers IDT specific features such as tracing and filtering.

Chapter 3, “CPS Switch Description,” covers the switch core behavior and flow control mechanism.

Chapter 4, “I2C Bus Interface,” describes the standard I2C bus interface implemented on the CPS.

Chapter 5, “Error Management,” explains the CPSs Error Management block. This block is responsible

for receiving, filtering, logging, counting, and responding to error reports from all of the functional blocks

within the device.

Chapter 6, “JTAG & Boundary Scan,” describes the CPS JTAG interface and code.

Chapter 7, “Reference Clock,” describes the reference clock requirement, system clock and SerDes clock

generation.

Chapter 8, “Programming the CPS,” provides the basic configure steps and rules.

Chapter 9, “CPS Reset & Initialization” provides reset and init steps.

Chapter 10, “Registers” provides the full memory map and complete listing of the CPS-16 registers,

Chapter 11, “References,” provides a list of all associated specifications referred to in this manual.

Documentation Conventions and Definitions

Throughout this manual the following conventions and terms are used:

To define the active polarity of a signal, signal names with and without overbars will be used. Signal

names with overbars are considered negative polarity or “active low” and are thus enabled when a

low voltage is applied.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will

be on the right. No leading zeros will be included.

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The

binary format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is

as follows: 0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

Unless otherwise denoted, a byte will refer to an 8-bit quantity. A word will refer to a 32-bit quantity,

and a double word will refer to an 8 Byte (64-bit) quantity. This is in accordance with RapidIO con-

About This Manual

IDT About This Manual

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Integrated Device Technology, Inc.

CPS-16/12/8 User Manual x July 10, 2012

vention.

A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

In double words, bit 63 is always the most significant bit and bit 0 is the least significant bit. In

words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is

always the most significant bit and bit 0 is the least significant bit.

This device follows the Big endian convention. The ordering of bytes within words is referred to as

either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (left-

most) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte

of a word.

Figure 1 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

A read-only: register, bit, or field is one which can be read but not modified

A sticky bit is a bit that remains set after being set by hardware until a zero is written to it. Writing a

one to a sticky has no effect on its value.

A zero field in a register, denoted as “0” in register figures, must be written with a value of zero and

returns a value of zero when read.

Revision History

July 10, 2012: Revision 1.5. Removed the confidential statements from the document’s footers.

January 19, 2011: Revision 1.4. Fixed a number of minor errors, updated I2C Interface, and added

notes to Packet Filtering and Multicast Packets

May 21, 2009: Revision 1.3. Fixed a number of minor errors.

January 19, 2009: Revision 1.2.

1. Add more detail about the Ack Counter and Nack Counter

2. Add basic device Programming example

3. Add detail explanation about the multicast respond

4. Add explanation about the multicast with responds

5. Add EPROM format example.

June 9, 2008: Revision 1.1.

Corrected switch chapter text around number of retries allowed for CRC error, as well as multicast

delaying discussion. Fixed /IRQ polarity in Error Handling chapter. Other editorial changes.

September 7, 2007: Initial release. Revision 1.0.

0123

bit 0bit 31

Address of Bytes within Words: Big Endian

3210

bit 0bit 31

Address of Bytes within Words: Little Endian

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