Ingenic X1000 Manuale del proprietario

X1000

IoTApplication Processor

Programming Manual

Release Date: Jan. 13, 2016

X1000 IoT Application Processor

Programming Manual

Disclaimer

This documentation is provided for use with Ingenic products. No license to Ingenic property rights is

granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the

usage, or intellectual property right infringement except as provided for by Ingenic Terms and

Conditions of Sale.

Ingenic products are not designed for and should not be used in any medical or life sustaining or

supporting equipment.

All information in this document should be treated as preliminary. Ingenic may make changes to this

document without notice. Anyone relying on this documentation should contact Ingenic for the current

documentation and errata.

Ingenic Semiconductor Co., Ltd.

Ingenic Headquarters, East Bldg. 14, Courtyard #10,

XIbeiwang East Road, Haidian District, Beijing 100193, China,

Tel: 86-10-56345000

Fax: 86-10-56345001

Http: //www.ingenic.com

CONTENTS

X1000 IoT Application Processor Programming Manual

CONTENTS

CONTENTS.............................................................................................i

TABLES...................................................................................................i

FIGURES.................................................................................................i

Section 1 Overview

1Overview .......................................................................................... 2

1.1 Block Diagram......................................................................................................................... 2

1.2 Features.................................................................................................................................. 2

1.2.1 CPU Core........................................................................................................................ 2

1.2.2 Image Core...................................................................................................................... 3

1.2.3 Display/Camera/Audio..................................................................................................... 3

1.2.4 Memory Interface ............................................................................................................ 5

1.2.5 System Functions............................................................................................................ 6

1.2.6 Peripherals ...................................................................................................................... 7

1.2.7 Bootrom........................................................................................................................... 9

Section 2 Core Functions

2CPU.................................................................................................11

2.1 Block Diagram........................................................................................................................11

2.2 Extra Features of the CPU core............................................................................................ 13

2.3 Instruction Cycles.................................................................................................................. 13

2.4PMON ................................................................................................................................... 16

2.4.1 Fundamental.................................................................................................................. 17

2.5 Partial Kernel Mode .............................................................................................................. 17

Section 3 Image Core

3JPEG.............................................................................................. 19

3.1 Overview............................................................................................................................... 19

3.2 Register Definition................................................................................................................. 19

3.2.1 Task trigger (TRIG)........................................................................................................ 19

3.2.2 VDMA status (STAT)...................................................................................................... 20

3.2.3 Global control information ............................................................................................. 20

3.2.4 JPGC trigger.................................................................................................................. 21

3.2.5 JPGC Status.................................................................................................................. 22

3.2.6 Bitstream buffer address ............................................................................................... 22

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X1000 IoT Application Processor Programming Manual

3.2.7 Component 0 plane buffer address ...............................................................................23

3.2.8 Component 1 plane buffer address ...............................................................................23

3.2.9 Component 2 plane buffer address ...............................................................................24

3.2.10 Component 3 plane buffer address ...............................................................................24

3.2.11 MCU number..................................................................................................................25

3.2.12 Re-Sync-Marker gap number ........................................................................................25

3.2.13 Component configure information..................................................................................25

3.2.14EFE control ....................................................................................................................26

3.2.15 Encoder slice geometry information ..............................................................................26

3.2.16 RAW plane source buffer address.................................................................................27

3.2.17 RAW destination buffer basement address ...................................................................27

3.2.18 RAW plane stride...........................................................................................................28

3.3 Table definition.......................................................................................................................28

3.3.1 Huffman Base Table.......................................................................................................28

3.3.2 Huffman MIN Table ........................................................................................................28

3.3.3 Quantization Table.........................................................................................................28

3.3.4 Huffman Symbol Table...................................................................................................29

3.3.5 Huffman ENC Table .......................................................................................................29

Section 4 Display/Camera/Audio

4SLCD Controller..............................................................................31

4.1 Overview................................................................................................................................31

4.2 Pin Description ......................................................................................................................31

4.3 Block Diagram.......................................................................................................................32

4.4 Register Description..............................................................................................................32

4.4.1 Configure Register (LCDCFG).......................................................................................35

4.4.2 Control Register (LCDCTRL).........................................................................................35

4.4.3 Status Register (LCDSTATE).........................................................................................36

4.4.4 OSD Control Register (LCDOSDCTRL)........................................................................37

4.4.5 Background0 Color Register (LCDBGC0).....................................................................37

4.4.6 Display Area Horizontal Start/End Point (LCDDAH)......................................................38

4.4.7 Display Area Vertical Start/End Point (LCDDAV)...........................................................38

4.4.8 Foreground 0 XY Position Register (LCDXYP0).........................................................38

4.4.9 Foreground 0 Size Register (LCDSIZE0) ...................................................................39

4.4.10 REV Signal Setting (LCDREV)......................................................................................39

4.4.11 Interrupt ID Register (LCDIID) .......................................................................................39

4.4.12 Descriptor Address Registers (LCDDAx).......................................................................40

4.4.13 Source Address Registers (LCDSA)..............................................................................41

4.4.14 Frame ID Registers (LCDFIDx) .....................................................................................42

4.4.15 DMA Command Registers (LCDCMDx) ........................................................................42

4.4.16 DMA OFFSIZE Registers (LCDOFFSx) ........................................................................43

4.4.17 DMA Page Width Registers (LCDPWx).........................................................................43

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X1000 IoT Application Processor Programming Manual

4.4.18 DMA Commend Counter Registers (LCDCNUMx) ....................................................... 44

4.4.19 DMA Commend Counter Registers (LCDCPOSx) ........................................................ 44

4.4.20 Foreground x Size in Descriptor (LCDDESSIZEx)........................................................ 45

4.4.21 Priority level threshold configure Register (LCDPCFG)................................................ 45

4.4.22 LCD Arbiter Priority(LCD_PCFG_ARB) ........................................................................ 46

4.4.23 SLCD Configure Register (MCFG)................................................................................ 47

4.4.24 SLCD Configure New Register (MCFG_NEW)............................................................. 48

4.4.25 SLCD Control Register (MCTRL).................................................................................. 51

4.4.26 SLCD Status Register (MSTATE).................................................................................. 52

4.4.27 SLCD Data Register (MDATA)...................................................................................... 52

4.4.28 SLCD Wait Time Register (WTIME).............................................................................. 53

4.4.29 Address Setup and Hold Time Register (TASH)........................................................... 53

4.4.30 Slow Mode Wait Time Register(SMWT)........................................................................ 53

4.5 SLCD Controller Operation................................................................................................... 54

4.5.1 Set SLCD Controller AHB Clock and Pixel Clock ......................................................... 54

4.5.2 Enabling the Controller.................................................................................................. 54

4.5.3 Disabling the Controller................................................................................................. 54

4.5.4 Resetting the Controller................................................................................................. 55

4.5.5 Frame Buffer.................................................................................................................. 55

4.6 System Memory Format........................................................................................................ 55

4.6.1 Data format.................................................................................................................... 55

4.6.2 Command Format ......................................................................................................... 57

4.7 Transfer Mode....................................................................................................................... 58

4.7.1 DMATransfer Mode ...................................................................................................... 58

4.7.2 Register Transfer Mode................................................................................................. 59

4.8 Timing ................................................................................................................................... 59

4.8.1 Parallel Timing............................................................................................................... 59

4.8.2 Serial Timing.................................................................................................................. 60

4.9 Operation Guide.................................................................................................................... 60

4.9.1 DMA Operation.............................................................................................................. 60

4.9.2 Register Operation ........................................................................................................ 61

5Camera Interface Module............................................................... 62

5.1 Overview............................................................................................................................... 62

5.1.1 Features ........................................................................................................................ 62

5.1.2 Pin Description .............................................................................................................. 62

5.2 CIM Special Register ............................................................................................................ 62

5.2.1 CIM Configuration Register (CIMCFG)......................................................................... 63

5.2.2 CIM Control Register (CIMCR) ..................................................................................... 66

5.2.3 CIM Control Register 2 (CIMCR2) ................................................................................ 67

5.2.4 CIM Status Register (CIMST)........................................................................................ 68

5.2.5 CIM Interrupt Mask Register (CIMIMR)......................................................................... 69

5.2.6 CIM Interrupt ID Register (CIMIID)................................................................................ 70

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X1000 IoT Application Processor Programming Manual

5.2.7 CIM Descriptor Address (CIMDA)..................................................................................71

5.2.8 CIM Frame buffer Address Register (CIMFA)................................................................71

5.2.9 CIM Frame ID Register (CIMFID)..................................................................................71

5.2.10 CIM DMA Command Register (CIMCMD).....................................................................72

5.2.11 CIM Window Size (CIMWSIZE).....................................................................................73

5.2.12 CIM Window Offset (CIMWOFFSET)............................................................................73

5.2.13 CIM Frame Size Register (CIMFS)................................................................................73

5.3 CIM Data Sample Modes ......................................................................................................74

5.3.1 Gated Clock Mode.........................................................................................................74

5.3.2 ITU656 Interlace Mode ..................................................................................................75

5.3.3 ITU656 Progressive Mode.............................................................................................76

5.4 DMA Descriptors....................................................................................................................76

5.5 Software Operation................................................................................................................77

5.5.1 Enable CIM with DMA....................................................................................................77

5.5.2 Operations for RXFIFO Overflow...................................................................................77

5.5.3 Operations for Frame Size Error....................................................................................77

6Audio Interface Controller................................................................79

6.1 Overview................................................................................................................................79

6.1.1 Block Diagram................................................................................................................80

6.1.2 Features.........................................................................................................................80

6.1.3 Interface Diagram ..........................................................................................................81

6.1.4 Signal Descriptions........................................................................................................82

6.2 Register Descriptions ............................................................................................................83

6.2.1 AIC Configuration Register (AICFR)..............................................................................84

6.2.2 AIC Common Control Register (AICCR) .......................................................................86

6.2.3 AIC I2S/MSB-justified Control Register (I2SCR)...........................................................89

6.2.4 AIC Controller FIFO Status Register (AICSR)...............................................................90

6.2.5 AIC I2S/MSB-justified Status Register (I2SSR).............................................................92

6.2.6 AIC I2S/MSB-justified Clock Divider Register (I2SDIV).................................................93

6.2.7 AIC FIFO Data Port Register (AICDR) ..........................................................................93

6.2.8 SPDIF Enable Register (SPENA)..................................................................................94

6.2.9 SPDIF Control Register (SPCTRL)................................................................................94

6.2.10 SPDIF State Register (SPSTATE) .................................................................................95

6.2.11 SPDIF Configure 1 Register (SPCFG1) ........................................................................96

6.2.12 SPDIF Configure 2 Register (SPCFG2) ........................................................................97

6.2.13 SPDIF FIFO Register (SPFIFO)....................................................................................98

6.3 Serial Interface Protocol........................................................................................................99

6.3.1 I2S and MSB-justified serial audio format .....................................................................99

6.3.2 Audio sample data placement in SDATA_IN/SDATA_OUT .........................................101

6.3.3 SPDIF Protocol............................................................................................................102

6.4 I2S Operation ......................................................................................................................103

6.4.1 Initialization..................................................................................................................103

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X1000 IoT Application Processor Programming Manual

6.4.2 External CODEC Registers Access Operation............................................................ 104

6.4.3 Audio Replay............................................................................................................... 104

6.4.4 Audio Record............................................................................................................... 105

6.4.5 FIFOs operation .......................................................................................................... 106

6.4.6 Data Flow Control........................................................................................................ 107

6.4.7 Audio Samples format................................................................................................. 108

6.4.8 Serial Audio Clocks and Sampling Frequencies ..........................................................110

6.4.9 Interrupts ......................................................................................................................114

6.5 SPDIF Guide........................................................................................................................115

6.5.1 Set SPDIF clock frequency ..........................................................................................115

6.5.2 PCM audio mode operation (Reference IEC60958) ....................................................115

6.5.3 Non-PCM mode operation (Reference IEC61937) ......................................................115

6.5.4 Disable operation .........................................................................................................116

7PCM Interface ...............................................................................117

7.1 Overview..............................................................................................................................117

7.2 Pin Description.....................................................................................................................117

7.3 Block Diagram......................................................................................................................118

7.4 Registers..............................................................................................................................118

7.4.1 Registers Memory Map................................................................................................119

7.4.2 Register Description.....................................................................................................119

7.5 PCM Interface Timing ......................................................................................................... 125

7.5.1 Short Frame SYN........................................................................................................ 125

7.5.2 Long Frame SYN......................................................................................................... 126

7.5.3 Multi-Slot Operation..................................................................................................... 126

7.6 PCM Operation ................................................................................................................... 127

7.6.1 PCM Initialization......................................................................................................... 127

7.6.2 Audio Replay............................................................................................................... 127

7.6.3 Audio Record............................................................................................................... 128

7.6.4 FIFOs operation .......................................................................................................... 128

7.6.5 Data Flow Control........................................................................................................ 129

7.6.6 PCM Serial Clocks and Sampling Frequencies .......................................................... 130

7.6.7 Interrupts ..................................................................................................................... 130

8Internal CODEC ........................................................................... 131

8.1 Overview............................................................................................................................. 131

8.2 Features.............................................................................................................................. 131

8.2.1 Signal Descriptions...................................................................................................... 132

8.2.2 Block Diagram............................................................................................................. 133

8.2.3 Application schematic.................................................................................................. 134

8.3 Mapped Register Descriptions............................................................................................ 134

8.3.1 CODEC internal register access control (RGADW).................................................... 135

8.3.2 CODEC internal register data output (RGDATA) ........................................................ 136

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X1000 IoT Application Processor Programming Manual

8.4 Operation.............................................................................................................................136

8.4.1 Access to internal registers of the embedded CODEC ...............................................137

8.4.2 CODEC controlling and typical operations ..................................................................137

8.4.3 Power saving ...............................................................................................................138

8.4.4 Pop noise and the reduction of it.................................................................................138

8.5 Timing parameters...............................................................................................................139

8.6 C parameters.......................................................................................................................140

8.7 CODEC internal Registers ..................................................................................................140

8.7.1 Registers Memory Map................................................................................................141

8.7.2 Register Description ....................................................................................................143

8.8 Programmable gains ...........................................................................................................174

8.8.1 Programmable boost gain: GIM...................................................................................174

8.8.2 Programmable input gain amplifier: GID .....................................................................175

8.8.3 Programmable digital attenuation: GOD......................................................................175

8.8.4 Programmable attenuation: GO...................................................................................176

8.8.5 Programmable digital mixer gain: GIMIX and GOMIX.................................................176

8.8.6 Gain refresh strategy ...................................................................................................177

8.9 Configuration of the headphone output stage.....................................................................177

8.10 Out-of-band noise filtering...................................................................................................178

8.10.1 Reset of short circuit detection ....................................................................................178

8.11 Sampling frequency: FREQ.................................................................................................178

8.12 Programmable data word length.........................................................................................179

8.13 Ramping system note..........................................................................................................179

8.14 AGC system guide ..............................................................................................................180

8.14.1 AGC operating mode...................................................................................................180

8.15DRC description ..................................................................................................................182

8.16 Digital Mixer description ......................................................................................................183

8.17 Digital microphone interface................................................................................................184

8.17.1 Timing Diagram............................................................................................................185

8.17.2 Timings.........................................................................................................................185

8.17.3 Noise template (TBC) ..................................................................................................186

8.17.4 Power Supply Noise Tolerance Template (PSNT2) on analog power supply for I/O

buffers of DAC outputs (VDDIO_CODEC)..................................................................................186

8.18 CODEC Operating modes...................................................................................................187

8.18.1 Initial all the gain..........................................................................................................188

8.18.2 Soft Mute mode............................................................................................................189

8.18.3 Power-down and sleep modes ....................................................................................190

8.18.4 Working modes summary............................................................................................191

8.19 MCLK turn-off and turn-on...................................................................................................192

8.20 Requirements on outputs and inputs selection and power-down modes............................192

8.20.1 Initialization and configuration .....................................................................................192

8.21 Circuits design suggestions.................................................................................................193

8.21.1 Avoid quiet ground common currents..........................................................................193

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X1000 IoT Application Processor Programming Manual

8.21.2 Microphone connection ............................................................................................... 194

8.21.3 PCB considerations..................................................................................................... 196

8.22 Analog characteristics......................................................................................................... 198

8.22.1 Operating conditions ................................................................................................... 198

8.22.2 With PWM output, used for analog amplifier application ............................................ 198

8.22.3

Microphone

Line

input

ADC path

.................................................................. 199

8.22.4

Micbias

and

reference

............................................................................................. 201

8.22.5

I/O buffers

................................................................................................................ 201

8.22.6

Characteristics

of the

ADC

High Pass

Filter

......................................................... 202

8.22.7

Characteristics

of the

ADC Wind Noise Filter

................................................... 202

Section 5 Memory Interface

9DDR Controller............................................................................. 204

9.1 Overview............................................................................................................................. 204

9.1.1 Supported DDR SDRAM Types .................................................................................. 204

9.1.2 Block Diagram............................................................................................................. 204

9.2 Register Description............................................................................................................ 205

9.2.1 DSTATUS.................................................................................................................... 208

9.2.2 DCFG .......................................................................................................................... 210

9.2.3 DCTRL......................................................................................................................... 212

9.2.4 DLMR .......................................................................................................................... 215

9.2.5 DTIMING1,2,3,4,5,6 (DDR Timing Configure Register).............................................. 216

9.2.6 DREFCNT (DDR Auto-Refresh Counter).................................................................... 220

9.2.7 DMMAP0,1 (DDR Memory Map Configure Register) ................................................. 221

9.2.8 DDLP (DDR DFI low power handshake control register)............................................ 222

9.2.9 DREMAP1,2,3,4,5 (DDR Address Remapping Register 1,2,3,4,5) ............................ 222

9.2.10 WCMDCTRL1 (Performance wcmd reorder & grouping)............................................ 224

9.2.11 RCMDCTRL0 (Performance rcmd request control).................................................... 225

9.2.12 RCMDCTRL1 (Performance rcmd request control).................................................... 226

9.2.13 BOUNDARYSEL (Channel boundary select).............................................................. 227

9.2.14 WDATTHD0 (performance wcmd request control)...................................................... 229

9.2.15 WDATTHD1 (performance wcmd request control)...................................................... 229

9.2.16 IPORTPRI (performance priority control).................................................................... 230

9.2.17 CHxQOS0,1,2,3,4,5 (performance QoS control) ........................................................ 231

9.2.18 AUTOSR_CNT............................................................................................................ 231

9.2.19 AUTOSR_EN............................................................................................................... 232

9.2.20 CLKSTP_CFG............................................................................................................. 232

9.2.21 DDRC_STATUS .......................................................................................................... 233

9.2.22 PHYRET_CFG ............................................................................................................ 233

9.2.23 PHYRST_CFG ............................................................................................................ 234

9.2.24 CPM_DRCG................................................................................................................ 234

9.3 Functional Description ........................................................................................................ 235

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X1000 IoT Application Processor Programming Manual

9.3.1 DDRC and DDR2 Memory Initialization Sequence .....................................................235

9.4 Change Clock Frequency....................................................................................................236

9.4.1 Manually SELF-REFRESH Mode................................................................................236

9.4.2 CPM driven SELF-REFRESH Mode............................................................................236

9.4.3 DLL bypass mode........................................................................................................236

9.5 Data Endian.........................................................................................................................237

9.6 Retention Flow.....................................................................................................................237

9.6.1 Enter Retention mode..................................................................................................237

9.6.2 Exit Retention mode ....................................................................................................238

10 SPI Flash Controller(SFC).............................................................242

10.1 Overview..............................................................................................................................242

10.2 Features ..............................................................................................................................242

10.3 Block Diagram.....................................................................................................................243

10.4 Functional Description.........................................................................................................243

10.4.1 Bus function.................................................................................................................243

10.4.2 Configurable Timing parameter ...................................................................................244

10.5 Pin Description ....................................................................................................................245

10.6 Data Format Description .....................................................................................................245

10.6.1 Transfer format ............................................................................................................245

10.6.2 Endian Description.......................................................................................................246

10.7 Registers Description ..........................................................................................................246

10.7.1 Instructions...................................................................................................................246

10.7.2 Map..............................................................................................................................247

10.7.3 Registers......................................................................................................................248

10.8 Software Guideline..............................................................................................................258

10.8.1 Phase Description........................................................................................................258

10.8.2 Multi phases flow .........................................................................................................259

10.8.3 One phase flow............................................................................................................259

10.8.4 Meters of DMA operation need attention.....................................................................260

10.8.5 Meters of slave mode operation need attention ..........................................................260

10.8.6 Example (NAND flash write with multi phases in DMA mode) ....................................260

10.8.7 Example (NAND flash write with single phase in REG mode) ....................................261

10.9 Index....................................................................................................................................263

Section 6 System Functions

11 Clock Reset and Power Controller ................................................265

11.1 Overview..............................................................................................................................265

11.1.1 CGU Block Diagram ....................................................................................................266

11.1.2 CGU Registers.............................................................................................................267

11.1.3 PLL Operation..............................................................................................................292

11.1.4 Main Clock Division Change Sequence ......................................................................294

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