Ingenic XBurst 2 CPU Core Manuale del proprietario

XBurst®2 CPU Core

Programming Manual

Release Date: June 2, 2017

XBurst®2 CPU Core

Programming Manual

Disclaimer

This documentation is provided for use with Ingenic products. No license to Ingenic property rights is

granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the

usage, or intellectual property right infringement except as provided for by Ingenic Terms and

Conditions of Sale.

Ingenic products are not designed for and should not be used in any medical or life sustaining or

supporting equipment.

All information in this document should be treated as preliminary. Ingenic may make changes to this

document without notice. Anyone relying on this documentation should contact Ingenic for the current

documentation and errata.

Ingenic Semiconductor Co., Ltd.

Ingenic Headquarters, East Bldg. 14, Courtyard #10

Xibeiwang East Road, Haidian District, Beijing, China,

Tel: 86-10-56345000

Fax:86-10-56345001

Http: //www.ingenic.com

CONTENTS

1Overview............................................................................................ 5

1.1 Features of XBurst®2 CPU for X2000.................................................................................... 5

2Operating Modes............................................................................... 6

3CP0.................................................................................................... 8

3.1 CP0 Register Summary.......................................................................................................... 8

3.1.1 CP0 Registers Grouped by Function .............................................................................. 8

3.1.2 CP0 Registers Grouped by Number ............................................................................. 10

3.2CP0 register Formats............................................................................................................ 12

3.2.1 CP0 Register Field Types.............................................................................................. 12

3.3 CP0 Register Descriptions.................................................................................................... 13

3.3.1CPU Configuration and Status Registers...................................................................... 13

3.3.2 TLB Management Registers ......................................................................................... 29

3.3.3 Exception Control Registers.......................................................................................... 38

3.3.4 Timer Registers............................................................................................................. 43

3.3.5 Cache Management Registers...................................................................................... 44

3.3.6 Thread Context and Shadow Control Registers ........................................................... 45

3.3.7 CPU Performance Monitor Registers............................................................................ 46

3.3.8 Debug Registers............................................................................................................ 48

3.3.9 User Mode Support Registers....................................................................................... 54

3.3.10 Kernel Mode Scratch Registers .................................................................................... 56

4Exceptions and Interrupts................................................................ 58

4.1 Exception Priority.................................................................................................................. 58

4.2 Exception Vector Locations................................................................................................... 59

4.3 Exception Handling Process................................................................................................. 60

4.3.1 Enter Exception Handler Routine.................................................................................. 60

4.3.2 Return from Exception Handler Routine....................................................................... 60

4.4 Exception Categories............................................................................................................ 61

5Memory Management Unit .............................................................. 63

5.1 Overview............................................................................................................................... 63

5.2 Virtual Memory Space........................................................................................................... 64

5.2.1 User Mode..................................................................................................................... 64

5.2.2 Kernel Mode.................................................................................................................. 65

5.3 TLB........................................................................................................................................ 67

5.3.1 Instruction Micro TLB .................................................................................................... 67

5.3.2 Data Micro TLB ............................................................................................................. 67

5.3.3 Variable Page Size TLB (VTLB).................................................................................... 67

XBurst®2 CPU Core Programming Manual

CONTENTS

5.3.4 Fixed Page Size TLB (FTLB).........................................................................................70

5.3.5 Filling JTLB Entry...........................................................................................................71

5.4 Virtual to Physical Address Translation.................................................................................72

6Caches.............................................................................................73

6.1 L1-cache................................................................................................................................73

6.1.1 Cache Coherency Attribute............................................................................................73

6.1.2 Cache Relative CP0 Registers......................................................................................74

6.1.3 Cache Operation Relative Instructions..........................................................................74

6.1.4 PREF/PREFX instruction...............................................................................................77

6.1.5 SYNC instruction ...........................................................................................................78

6.2 L2-cache................................................................................................................................79

7Initialize Core State..........................................................................80

7.1 Initialized Core State by Hardware........................................................................................80

7.1.1 Coprocessor 0 State......................................................................................................80

7.1.2 TLB Initialization.............................................................................................................80

7.1.3 Cache Initialization.........................................................................................................80

7.2 Initialized Core State by Software.........................................................................................80

7.2.1 General Purpose Registers Initialization .......................................................................80

8CCU..................................................................................................81

8.1 Overview................................................................................................................................81

8.2 Register Description..............................................................................................................82

8.2.1 Cores SLeep Control Register.......................................................................................83

8.2.2 Core Sleep Status Register...........................................................................................84

8.2.3 Core Software Reset Register.......................................................................................85

8.2.4 Memory Subsystem Control Register............................................................................86

8.2.5 Memory Subsystem Implementation Register...............................................................87

8.2.6 CPU Configuration Register ..........................................................................................88

8.2.7 Peripheral IRQ Pending Register ..................................................................................89

8.2.8 Peripheral IRQ Mask Register.......................................................................................89

8.2.9 Mailbox IRQ Pending Register ......................................................................................90

8.2.10 Mailbox IRQ Mask Register...........................................................................................90

8.2.11 OST IRQ Pending Register ...........................................................................................91

8.2.12 OST IRQ Mask Register................................................................................................91

8.2.13 Debug Interrupt Pending Register.................................................................................92

8.2.14 Debug Interrupt Mask Register......................................................................................92

8.2.15 Reset Entry Register......................................................................................................93

8.2.16 Mailbox Register<N>.....................................................................................................93

8.2.17 CCU Spin Lock Register................................................................................................94

8.2.18 CCU Spin Atomic Register.............................................................................................94

8.2.19 Global Interrupt Mask Register......................................................................................95

XBurst®2 CPU Core Programming Manual

CONTENTS

8.2.20 CPU Feature Configuration Register ............................................................................ 96

8.2.21 Bus Exception Control Register.................................................................................... 97

8.3 Usage.................................................................................................................................... 98

8.3.1 The Configuration of CCU............................................................................................. 98

9EJTAG Debug Support.................................................................... 99

9.1 Overview............................................................................................................................... 99

9.2 Detecting Debug Mode....................................................................................................... 100

9.3 Ways of Entering Debug Mode........................................................................................... 100

9.4 Exiting Debug Mode............................................................................................................ 100

9.5 Hardware Breakpoints ........................................................................................................ 100

9.5.1 Instruction Breakpoints................................................................................................ 101

9.5.2 Data Breakpoints......................................................................................................... 101

9.5.3 Overview of Instruction Breakpoint Registers............................................................. 101

9.5.4 Overview of Data Breakpoint Registers...................................................................... 101

9.6 Conditions for Matching Breakpoints.................................................................................. 102

9.6.1 Conditions for Matching Instruction Breakpoints......................................................... 102

9.6.2 Conditions for Matching Data Breakpoints.................................................................. 102

9.6.3 SIMD Load/Store Handling.......................................................................................... 103

9.7 Debug Exceptions from Breakpoints .................................................................................. 103

9.7.1 Debug Exception by Instruction Breakpoint................................................................ 104

9.7.2 Debug Exception by Data Breakpoint......................................................................... 104

9.7.3 Breakpoint Used as Triggerpoint................................................................................. 104

9.8 Test Access Port (TAP) ....................................................................................................... 104

9.8.1 EJTAG Internal and External Interfaces...................................................................... 105

9.8.2 Test Access Port Operation......................................................................................... 105

9.8.3 Test Access Port (TAP) Instructions............................................................................ 109

9.8.4 TAP Processor Accesses .............................................................................................111

9.9 EJTAG Registers .................................................................................................................113

9.9.1 General Purpose Control and Status...........................................................................113

9.9.2 Instruction Breakpoint Registers..................................................................................114

9.9.3 Data Breakpoint Registers ...........................................................................................117

9.9.4 EJTAG TAP Registers................................................................................................. 122

9.10 Debug Exception................................................................................................................. 130

9.10.1 Debug Exception Priorities.......................................................................................... 130

9.10.2 Debug Exception Vector Location............................................................................... 131

9.10.3 General Debug Exception Processing........................................................................ 131

9.10.4 Debug Single Step Exception ..................................................................................... 132

9.10.5 Debug Interrupt Exception........................................................................................... 133

9.10.6 Debug Instruction Break Exception............................................................................. 133

9.10.7 Debug Breakpoint Exception....................................................................................... 133

9.10.8 Debug Data Break on Load/Store Exception.............................................................. 134

9.11 Debug Mode Exceptions..................................................................................................... 134

XBurst®2 CPU Core Programming Manual

iii

CONTENTS

9.11.1 Exceptions Taken in Debug Mode...............................................................................134

9.11.2 Debug Mode Exception Processing ............................................................................135

9.12 MIPS EJTAG Compliant Mode............................................................................................136

9.13 Accelerated EJTAG Mode...................................................................................................136

9.13.1 ACC Mode Flag ...........................................................................................................136

9.13.2 EJTAG Control Register in ACC mode (ECR_A).........................................................136

9.13.3 Processor Access Address Register in ACC mode (ADDRESS_A)............................138

9.13.4 Processor Access Data Register in ACC mode (DATA_A)..........................................138

9.13.5 Debug ModeAddress Space in Compliant Mode (AM = 0).........................................139

9.13.6 Debug ModeAddress Space in ACC Mode (AM = 1)..................................................139

9.13.7 Supported JTAG Instructions in ACC Mode ................................................................140

Revision History...................................................................................141

XBurst®2 CPU Core Programming Manual

Operating Modes

1 Overview

XBurst®2 CPU is a high performance and low power implementation of MIPS32 ISAr5 + Configurable

SIMD ISA (MIPS MSA128 + XBurst® MXA128 for X2000) instruction set architecture.

1.1 Features of XBurst®2 CPU for X2000

32-bit MIPS32 ISA R5 plus MIPS SIMD instruction set architecture:MSA128

Ingenic SIMD instruction set architecture: MXA128

dual-issue, superscalar, super pipeline with Simultaneous Multi-Threading (SMT)

Two hardware threads per physical core

Quad instructions fetch per cycle

Dual-issue instructions per hardware thread per cycle

Smart branch prediction scheme with Instruction trace buffer (ITB), Branch Target Buffer

(BTB), Pattern History Table (PHT), Return Address Stack (RAS) and Jump Target Buffer

(RTB)

L1 cache size up to 32KB for Instruction cache and Data cache, respectively, 8-way set

associative

high-performance dual-issue floating-point (single and double) and 128-bit SIMD Unit

32 x 128-bit registers, 128-bit loads/stores to/from SIMD unit

data types: 8/16/32 bits integer, Q15/Q31 fixed point and 32/64 bits floating point

IEEE-754 2008 compliance

Programmable Memory Management Unit (MMU)

1st level mini-TLB (MTLB): 8-entry instruction MTLB, 16-entry data MTLB

2nd level joint TLBs: 32-entry VTLB, 256-entry 4-way set associative FTLB

Integrated Cache Crossbar (CCX) and L2 cache

Configurable size up to 1MB

Support multi-core configurations up to 4 physical cores (4 cores with total 8 threads)

Hardware prefetcher for streaming performance

Advanced power management

Hardware automatic clock gating for idle subsystems

XBurst2 CPU implements SMT technology - a physical core contains 2 simultaneous threads. For

convenience of description, a thread can be regarded as a logic core. Therefore, except explicitly

claim, a core means a logic core in later chapters.

XBurst®2 CPU Core Programming Manual

Overview

2 Operating Modes

XBurst®2 CPU core supports three operating modes:

Debug Mode

Kernel Mode

User Mode

Table 2-1 the conditions of operating mode

Debug.DM Status.UM Status.EXL Status.ERL Operating Mode

1 X X X Debug Mode

0 0 X X Kernel Mode

0 X 1 X

0 X X 1

0 1 0 0 User Mode

X denotes don't care.

XBurst®2 CPU Core Programming Manual

CP0

3 CP0

The XBurst2 System Control Coprocessor (CP0) provides the register interface to the XBurst2 core

and supports memory management, address translation, exception handling, and other privileged

operations. Each CP0 register has a unique number that identifies it, referred to as its register number.

A separate select number is used to differentiate additional registers within the register number. For

example, as shown in the table below, there are eight configuration registers with register number 16.

If the select number is omitted, it is zero.

This chapter contains the following sections:

• Section 3.1 “CP0 Register Summary”

• Section 3.2 “CP0 Register Formats”

• Section 3.3 “CP0 Register Descriptions”

3.1 CP0 Register Summary

The following two subsections show the CP0 register set, Table 3-1 CP0 Register Grouped by

Function and Table 3-2 CP0 Registers Grouped by Number.

3.1.1 CP0 Registers Grouped by Function

The CP0 registers set are divided into several register groups listed below.

Table 3-1 CP0 Register Grouped by Function

Category Register

Name Register

Number Register

Select

CPU Configuration

and Status Config 16 0 section 3.3.1.1

Config1 16 1 section 3.3.1.2

Config2 16 2 section 3.3.1.3

Config3 16 3 section 3.3.1.4

Config4 16 4 section 3.3.1.5

Config5 16 5 section 3.3.1.6

PRId 15 0 section 3.3.1.7

EBase 15 1 section 3.3.1.8

Status 12 0 section 3.3.1.9

IntCtl 12 1 section 3.3.1.10

TLB Management Index 0 0 section 3.3.2.1

Random 1 0 section 3.3.2.2

EntryLo0 2 0 section 3.3.2.3

EntryLo1 3 0 section 3.3.2.3

EntryHi 10 0 section 3.3.2.4

Context 4 0 section 3.3.2.5

PageMask 5 0 section 3.3.2.6

PageGrain 5 1 section 3.3.2.7

Wired 6 0 section 3.3.2.8

XBurst®2 CPU Core Programming Manual

Indice

Altri manuali Ingenic Hardware per computer

Ingenic

Ingenic JZ4775 Guida

Ingenic

Ingenic Halley5 Manuale utente

Ingenic

Ingenic JZ4780 Manuale del proprietario

Ingenic

Ingenic JZ4780 Guida

Ingenic

Ingenic X1000 Manuale del proprietario

Manuali Hardware per computer popolari di altre marche

EMC2

EMC2 VNX Series Manuale del proprietario

Panasonic

Panasonic DV0PM20105 Manuale utente

Mitsubishi Electric

Mitsubishi Electric Q81BD-J61BT11 Manuale utente

Gigabyte

Gigabyte B660M DS3H AX DDR4 Manuale utente

Raidon

Raidon iT2300 Manuale utente

National Instruments

National Instruments PXI-8186 Manuale utente

Hauppauge

Hauppauge WinTV-HVR-2250 Manuale utente

Kontron

Kontron CP6002 Manuale utente

Manhattan

Manhattan 702843 Manuale utente

Aphex

Aphex 230 Manuale utente

AMD

AMD Phenom II Manuale operativo

Intel

Intel NUC 12 Pro Manuale utente

dbx

dbx Zone Pro 1260 Manuale utente

Galaxy

Galaxy GHDX2-2430S-24F4D Manuale utente

Intel

Intel AXXRMFBU4 Manuale utente

Kontron

Kontron DIMM-PC/MD Manuale utente

ST X-NUCLEO-SAFEA1B Istruzioni operative

STEINWAY LYNGDORF

STEINWAY LYNGDORF SP-1 Manuale utente