Intel Cyclone V Manuale di istruzioni
Contents
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC
FPGAs........................................................................................................................ 4
1.1. The SoC FPGA Designer’s Checklist.......................................................................... 5
1.2. Overview of HPS Design Guidelines for SoC FPGA design.............................................7
1.3. Overview of Board Design Guidelines for SoC FPGA Design..........................................8
1.4. Overview of Embedded Software Design Guidelines for SoC FPGA Design...................... 9
2. Background: Comparison between Cyclone V SoC FPGA and Arria V SoC FPGA HPS
Subsystems............................................................................................................. 10
2.1. Guidelines for Interconnecting the HPS and FPGA.....................................................10
2.1.1. HPS-FPGA Bridges....................................................................................10
2.1.2. FPGA-to-HPS SDRAM Access......................................................................12
2.1.3. Connecting Soft Logic to HPS Component....................................................14
3. Design Guidelines for HPS portion of SoC FPGAs...........................................................15
3.1. Start your SoC-FPGA design here...........................................................................15
3.1.1. Recommended Starting Point for HPS-to-FPGA Interface Design..................... 15
3.1.2. Determining your SoC FPGA Topology......................................................... 15
3.2. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory.........16
3.2.1. HPS Pin Assignment Design Considerations..................................................17
3.2.2. HPS I/O Settings: Constraints and Drive Strengths....................................... 18
3.3. HPS Clocking and Reset Design Considerations........................................................ 19
3.3.1. HPS Clock Planning.................................................................................. 20
3.3.2. Early Pin Planning and I/O Assignment Analysis........................................... 20
3.3.3. Pin Features and Connections for HPS JTAG, Clocks, Reset and PoR ............... 20
3.3.4. Internal Clocks........................................................................................ 21
3.4. HPS EMIF Design Considerations............................................................................21
3.4.1. Considerations for Connecting HPS to SDRAM.............................................. 21
3.4.2. HPS SDRAM I/O Locations.........................................................................23
3.4.3. Integrating the HPS EMIF with the SoC FPGA Device.....................................23
3.4.4. HPS Memory Debug................................................................................. 23
3.5. DMA Considerations............................................................................................. 24
3.5.1. Choosing a DMA Controller........................................................................ 24
3.5.2. Optimizing DMA Master Bandwidth through HPS Interconnect........................ 24
3.5.3. Timing Closure for FPGA Accelerators......................................................... 24
3.6. Managing Coherency for FPGA Accelerators............................................................. 25
3.6.1. Cache Coherency..................................................................................... 25
3.6.2. Coherency between FPGA Logic and HPS: Accelerator Coherency Port (ACP).... 25
3.6.3. Data Size Impacts ACP Performance........................................................... 25
3.6.4. FPGA Access to ACP via AXI or Avalon-MM...................................................26
3.6.5. Data Alignment for ACP and L2 Cache ECC accesses..................................... 26
3.7. IP Debug Tools.................................................................................................... 26
4. Board Design Guidelines for SoC FPGAs........................................................................ 28
4.1. Board Bring Up Considerations...............................................................................28
4.1.1. Reserved BSEL Setting............................................................................. 28
4.2. Boot and Configuration Design Considerations......................................................... 28
4.2.1. Boot Design Considerations....................................................................... 28
Contents
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4.2.2. Configuration.......................................................................................... 32
4.2.3. Reference Materials..................................................................................32
4.3. HPS Power Design Considerations.......................................................................... 32
4.3.1. Early System and Board Planning...............................................................33
4.3.2. Design Considerations for HPS and FPGA Power Supplies for SoC FPGA
devices...................................................................................................34
4.3.3. Pin Connection Considerations for Board Designs..........................................34
4.3.4. Power Analysis and Optimization................................................................ 35
4.4. Boundary Scan for HPS.........................................................................................36
4.5. Design Guidelines for HPS Interfaces...................................................................... 36
4.5.1. HPS EMAC PHY Interfaces......................................................................... 36
4.5.2. USB Interface Design Guidelines................................................................ 43
4.5.3. QSPI Flash Interface Design Guidelines....................................................... 44
4.5.4. SD/MMC and eMMC Card Interface Design Guidelines................................... 45
4.5.5. NAND Flash Interface Design Guidelines......................................................46
4.5.6. UART Interface Design Guidelines...............................................................46
4.5.7. I2C Interface Design Guidelines..................................................................47
4.5.8. SPI Interface Design Guidelines................................................................. 47
5. Embedded Software Design Guidelines for SoC FPGAs.................................................. 49
5.1. Embedded Software for HPS: Design Guidelines.......................................................49
5.1.1. Assembling the Components of Your Software Development Platform..............49
5.1.2. Selecting an Operating System for Your Application...................................... 52
5.1.3. Assembling your Software Development Platform for Linux............................ 53
5.1.4. Assembling a Software Development Platform for a Bare-Metal Application...... 57
5.1.5. Assembling your Software Development Platform for a Partner OS or RTOS..... 58
5.1.6. Choosing Boot Loader Software................................................................. 58
5.1.7. Selecting Software Tools for Development, Debug and Trace.......................... 60
5.2. Flash Device Driver Design Considerations.............................................................. 61
5.3. HPS ECC Design Considerations............................................................................. 61
5.3.1. General ECC Design Considerations............................................................ 62
5.3.2. System-Level ECC Control, Status and Interrupt Management........................62
5.3.3. ECC for L2 Cache Data Memory................................................................. 62
5.3.4. ECC for Flash Memory.............................................................................. 63
5.4. HPS SDRAM Considerations...................................................................................63
5.4.1. Using the Preloader To Debug the HPS SDRAM............................................. 63
5.4.2. Access HPS SDRAM via the FPGA-to-SDRAM Interface...................................67
A. Support and Documentation......................................................................................... 69
A.1. Support..............................................................................................................69
A.2. Software Documentation.......................................................................................70
B. Additional Information................................................................................................. 71
B.1. Cyclone V and Arria V SoC Device Guidelines Revision History....................................71
Contents
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1. Overview of the Design Guidelines for Cyclone® V SoC
FPGAs and Arria® V SoC FPGAs
The purpose of this document is to provide a set of design guidelines and
recommendations, as well as a list of factors to consider, for designs that use the
Cyclone V SoC and Arria V SoC FPGA devices. This document assists you in the
planning and early design phases of the SoC FPGA design, Platform Designer
(Standard) sub-system design, board design and software application design.
Note: This application note does not include all the Cyclone V/Arria V Hard Processor System
(HPS) device details, features or information on designing the hardware or software
system. For more information about the Cyclone V or Arria V HPS features and
individual peripherals, refer to the respective Hard Processor System Technical
Reference Manual.
Design guidelines for the FPGA portion of your design are provided in the Arria V and
Cyclone V Design Guidelines.
Related Information
•Arria V Hard Processor System Technical Reference Manual
•Cyclone V Hard Processor System Technical Reference Manual
•Intel MAX 10 FPGA Design Guidelines
AN-796 | 2018.06.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
1.1. The SoC FPGA Designer’s Checklist
Table 1. The SoC FPGA Designer's Checklist
Step Title Links Check (X)
HPS Designer's Checklist for SoC FPGAs
Start your SoC FPGA Design here Start your SoC-FPGA design here on page 15
Determining your SoC FPGA Topology on page 15
Design Considerations for Connecting
Device I/O to HPS Peripherals and
Memory
HPS Pin Assignment Design Considerations on page 17
HPS I/O Settings: Constraints and Drive Strengths on page 18
HPS Clocking and Reset Design
Considerations
HPS Clock Planning on page 20
Early Pin Planning and I/O Assignment Analysis on page 20
Pin Features and Connections for HPS JTAG, Clocks, Reset and PoR
on page 20
Internal Clocks on page 21
HPS EMIF Design Considerations Considerations for Connecting HPS to SDRAM on page 21
HPS SDRAM I/O Locations on page 23
Integrating the HPS EMIF with the SoC FPGA Device on page 23
HPS Memory Debug on page 23
DMA Considerations Choosing a DMA Controller on page 24
Optimizing DMA Master Bandwidth through HPS Interconnect on page
24
Timing Closure for FPGA Accelerators on page 24
Managing Coherency for FPGA
Accelerators
Cache Coherency on page 25
Coherency between FPGA Logic and HPS: Accelerator Coherency Port
(ACP) on page 25
Data Size Impacts ACP Performance on page 25
FPGA Access to ACP via AXI or Avalon-MM on page 26
Data Alignment for ACP and L2 Cache ECC accesses on page 26
IP Debug Tools IP Debug Tools on page 26
Board Designer's Checklist for SoC FPGAs
HPS Power Design Considerations Early System and Board Planning on page 33
Early Power Estimation on page 33
Design Considerations for HPS and FPGA Power Supplies for SoC
FPGA devices on page 34
Pin Connection Considerations for Board Designs on page 34
Device Power-Up on page 34
Power Analysis and Optimization on page 35
Boundary Scan for HPS Boundary Scan for HPS on page 36
Design Guidelines for HPS Interfaces HPS EMAC PHY Interfaces on page 36
continued...
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
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Step Title Links Check (X)
USB Interface Design Guidelines on page 43
QSPI Flash Interface Design Guidelines on page 44
SD/MMC and eMMC Card Interface Design Guidelines on page 45
NAND Flash Interface Design Guidelines on page 46
UART Interface Design Guidelines on page 46
I2C Interface Design Guidelines on page 47
SPI Interface Design Guidelines on page 47
Embedded Software Designer's Checklist for SoC FPGAs
Assemble the components of your
Software Development Platform
Assembling the Components of Your Software Development Platform
on page 49
Golden Hardware Reference Design on page 50
Select an Operating System (OS) for
your application
Linux or RTOS on page 52
Bare Metal on page 52
Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP)
Modes on page 53
Assemble your Software
Development Platform for Linux
Golden System Reference Design (GSRD) for Linux on page 54
GSRD for Linux Development Flow on page 54
GSRD for Linux Build Flow on page 55
Linux Device Tree Design Considerations on page 56
Assemble your Software
Development Platform for Bare-metal
Application
Assembling a Software Development Platform for a Bare-Metal
Application on page 57
Assemble your Software
Development Platform for Partner
OS/RTOS Application
Assembling your Software Development Platform for a Partner OS or
RTOS on page 58
Choose the Boot Loader Software Choosing Boot Loader Software on page 58
Selecting Software Tools for
Development, Debug and Trace
Select Software Build Tools on page 60
Select Software Debug Tools on page 60
Select Software Trace Tools on page 61
Board Bring Up Considerations Board Bring Up Considerations on page 28
Boot and Configuration Design
Considerations
Boot Design Considerations on page 28
Configuration on page 32
Flash Device Driver Considerations Flash Device Driver Design Considerations on page 61
HPS ECC Design Considerations HPS ECC Design Considerations on page 61
HPS SDRAM Considerations HPS SDRAM Considerations on page 63
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
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1.2. Overview of HPS Design Guidelines for SoC FPGA design
Table 2. HPS Design Guidelines Overview
Stages of the HPS Design Flow Guidelines Links
Hardware and Software Partitioning Determine your system topology and
use it as a starting point for your HPS
to FPGA interface design.
Guidelines for Interconnecting the HPS
and FPGA on page 10
HPS Pin Multiplexing and I/O
Configuration Settings
Plan configuration settings for the HPS
system including I/O multiplexing
options, interface to FPGA and SDRAM,
clocks, peripheral settings
Design Considerations for Connecting
Device I/O to HPS Peripherals and
Memory on page 16
HPS Clocks and Reset Considerations HPS clocks and cold and warm reset
considerations
HPS Clocking and Reset Design
Considerations on page 19
HPS EMIF Considerations Usage of the HPS EMIF controller and
related considerations
HPS EMIF Design Considerations on
page 21
FPGA Accelerator Design
Considerations
Design considerations to manage
coherency between FPGA accelerators
and the HPS
DMA Considerations on page 24
Recommended Tools for IP
Development
Signal Tap II, BFMs, System Console IP Debug Tools on page 26
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
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1.3. Overview of Board Design Guidelines for SoC FPGA Design
Table 3. Board Design: Design Guidelines Overview
Stages of the Board Design Flow Guidelines Links
HPS Power design considerations Power on board bring up, early power
estimation, design considerations for
HPS and FPGA power supplies, power
analysis and power optimization
HPS Power Design Considerations on
page 32
Board design guidelines for HPS
interfaces
Includes EMAC, USB, QSPI, SD/MMC,
NAND, UART and I2C
Design Guidelines for HPS Interfaces
on page 36
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
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1.4. Overview of Embedded Software Design Guidelines for SoC
FPGA Design
Table 4. Embedded Software: Design Guidelines Overview
Stages of the Embedded Software
Design Flow
Guidelines Links
Operating System (OS) considerations OS considerations to meet your
application needs, including real time,
software reuse, support and ease of
use considerations
Selecting an Operating System for Your
Application on page 52
Boot Loader considerations Boot loader considerations to meet
your application needs. including GPL
requirements, and features.
Choosing Boot Loader Software on
page 58
Boot and Configuration Design
Considerations
Boot source, boot clock, boot fuses,
configuration flows
Boot and Configuration Design
Considerations on page 28
HPS ECC Considerations ECC for external SDRAM interface, L2
cache data memory, flash memory
HPS ECC Design Considerations on
page 61
HPS SDRAM Considerations Using Preloader to debug HPS SDRAM,
Accessing the HPS SDRAM
HPS SDRAM Considerations on page
63
1. Overview of the Design Guidelines for Cyclone® V SoC FPGAs and Arria® V SoC FPGAs
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2. Background: Comparison between Cyclone V SoC FPGA
and Arria V SoC FPGA HPS Subsystems
While the HPS subsystems in Cyclone V SoC and Arria V SoC are architecturally
similar, there are a few differences in features as listed below.
HPS Features Cyclone V SoC Arria V SoC
Maximum MPU Frequency Up to 925 MHz Up to 1.05 GHz
Controller Area Network (CAN) Yes No
Total HPS Dedicated I/O with Loaner capability Up to 67 94 (1)
Automotive Grade Option Yes No
Maximum supported DDR3 Frequency for HPS SDRAM 400 MHz 533 MHz
Related Information
Differences Among Intel SoC Device Families
2.1. Guidelines for Interconnecting the HPS and FPGA
The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial
tool to maximize the performance of your design.
Design guidelines for the FPGA portion of your design are provided in the Arria V and
Cyclone V Design Guidelines.
Related Information
Arria V and Cyclone V Design Guidelines
2.1.1. HPS-FPGA Bridges
The HPS has three bridges that use memory-mapped interfaces to the FPGA based on
the Arm* Advanced Microcontroller Bus Architecture (AMBA*) Advanced eXtensible
Interface (AXI*). Their purpose determines the direction of each bridge.
(1) You can only assign a maximum of 71 HPS I/O as Loaner I/O to the FPGA. For a detailed
comparison between the HPS subsystem for Cyclone V SoC and Arria V SoC, refer to
Differences Among Intel SoC Device Families.
AN-796 | 2018.06.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
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