ITE IT6506 Istruzioni operative

IT6506 Programming Guide

Ver 1.02

Tseng Jau-Chih

ITE Tech. INC.

Last Update Date: 2013/11/12

History

-i

Index

Chap 1

Introduce .......................................................................................................... 1

Chap 2

IT6506 Initial..................................................................................................... 4

Initial Register Setting ...................................................................................................................4

Chap 3

Event of IT6506 ................................................................................................ 6

Chap 4

Link Configuration ............................................................................................ 8

Hot Plug ........................................................................................................................................8

System status................................................................................................................................8

IT6506 Capacity Configuring.........................................................................................................8

Detecting a Tx...............................................................................................................................8

Training .........................................................................................................................................8

Train Fail .......................................................................................................................................8

Chap 5

Video Programming.......................................................................................... 9

Video Input Readback...................................................................................................................9

Video Output Programming.........................................................................................................10

Output RGB444 video ............................................................................................................. 11

Output YCbCr444 video .......................................................................................................... 11

Output YCbCr422 video sync seperated................................................................................. 11

Output YCbCr422 video sync embedded................................................................................12

Output YCbCr422 video sync embedded CCIR656 ................................................................12

Color Converting .....................................................................................................................13

Enable Video Output ................................................................................................................... 14

Chap 6

Audio Programming........................................................................................ 15

Audio Input Information............................................................................................................... 15

Configure Audio Output............................................................................................................... 16

Audio Error..................................................................................................................................16

Chap 9

Registers ........................................................................................................ 19

Bank 0 : reg05[3] = ‘0’, reg05[0] = ‘0’ ..........................................................................................19

Bank 1 : Reg05[3][0] = ‘0’ ‘1’ .......................................................................................................31

Bank 2 : (reg5[3] = ‘1’, reg5[0] = ‘0’)............................................................................................ 37

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -1- 2013/11/12

Chap 1 Introduce

The IT6506 is a high-performance DisplayPort 1.1a receiver, fully compliant with DisplayPort

1.1a,

HDCP 1.3 specifications. The IT6506 with its Deep Color capability (up to 36-bit) ensures

robust reception of high-quality uncompressed video content, along with state-of-the-art

uncompressed and compressed digital audio content.

Aside from the various video output formats supported, the IT6506 also receives and provides

up to 8 channels of I

S digital audio outputs, with sampling rate up to 192kHz and sample size

up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an

S/PDIF output is provided to support up to compressed audio of 192kHz frame rate.

Each IT6506 comes preprogrammed with an unique HDCP key, in compliance with the HDCP

1.3 standard so as to provide secure transmission of high-definition content. Users of the

IT6506 need not purchase any HDCP keys or ROMs.

Features

•Compliance with DisplayPort Specification V1.1a at 1.62/2.7 Gbps data rate (Low bit

rate/High bit rate)

•Support flexible 1/2/4 lanes configurations; Full 10.8Gbps data rate support(4 lanes at

2.7Gbps)

•Support DPCD Rev.1.1

•Support HDCP 1.3 with HDCP key embedded

•Support Spread Spectrum Clocking up to 0.5% down-spread to reduce EMI

•Support Source Connection Detection through AUX channel DC levels

•Support up to WQXGA(2560X1600) VESA display format

•Support Digital Video Output in 18/24/30/36(deep color) bits format with separate

Sync control

•Support Pixel component format with RGB; YCbCr 422; YCbCr 444

•Support Bit depth per color with 6/8/10/12 bits

•Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces

with programmable coefficients.

•Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2

•Dithering for conversion from 12-bit component to 10-bit/8-bit

•S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio up to 192kHz frame

rate

•Support 8-channel, uncompressed LPCM I2S audio with sample rates of 32~192 kHz

and sample sizes of 16~24 bits

•Automatic Audio Error detection with soft mute function, preventing annoying harsh

output sound due to audio error or hot-unplug

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -2- 2013/11/12

•Automatic loss of signal detection for Link management

•Intelligent, programmable power management

•144-pin LQFP (20mm x 20mm) package

Pin Diagram

37383940414243444546474849505152535455565758596061

6263646566676869707172

IT6506

Displayport RX Chip

LQFP-144

(Top View)

I2S2

I2S0

DCAUXN

DCAUXP

RX3N

RX3P

RX2N

RX2P

AVCC

AGND

RX1N

RX1P

AVCC

RX0N

RX0P

DVDD18

PGND

PVCC

ASPGND

ASPVCC

RXAUXP

RXAUXN

XTALIN

XTALOUT

INT#

PCADR

I2S3

ENTEST

PGND

PVCC

I2S1

SCLK

EMEM_VPP

PCSCL

PCSDA

QB2

QB3

QB6

QB7

QB8

QB9

QB5

QB4

IVSS

HPD

IVDD

MCLK

SPDIF

OVDD

OVSS

OVDD

OVSS

QA20

QA21

QA26

QA27

QA28

IVDD

IVSS

QA30

QA31

OVDD

OVSS

QA22

QA23

QA24

QA25

QA32

QA35

DVSS18

DVDD18

AGND

AVCC

DVSS18

QA33

QA34

QA29

SYSRSTN

OVSS

QB10

QB11 QA16

QA17

QA18

QA19

OVDD

QB21

QB20

144143142141140139138137136135134133132131130129128127126125124123122121120

101

102

103

104

105

106

107

108

119118117116115114113112111110109

QB14

QB15

QB16

QB17

QB18

QB19

DDCSDA

DDCSCL

IVDD

IVSS

VSYNC

HSYNC

IVDD

PCLK

IVSS

QA0

QA1

QA4

QA5

OVDD

OVSS

QA2

QA3

QB35

OVSS

QB26

QB27

IVDD

IVSS

QB28

QB29

QB30

QB31

QB32

QB33

QB34

OVSS

QB23

OVDD

QB22

QA8

QA9

QA10

QA11

QA12

QA13

QA14

QA15

IVDD

IVSS

100

QA6

QA7

IT6506 provides internal register accessed via PCSCL (pin 71) and PCSDA (pin 70) with slave

address 0xB0 where PCADR (pin68) is low, or 0xB2 where PCADR (pin68) is high under

100KHz speed.

The terms listed in the below table are using in future chapters:

Term Description Example

RegXX Where XX is a hexadecimal number, to indicate the

internal register accessed with subaddress XX of

C, and in ban 0.

Reg05 – access with I

C slave

address 0xB0/0xB2,

sub-address 0x05.

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -3- 2013/11/12

Reg1XX

Where XX is a hexadecimal number, to indicate the

internal register accessed with subaddress XX of

C, and in ban 1.

Reg1C0 – access with I

slave address 0xB0/0xB2,

sub-address 0xC0.

Reg2XX

Where XX is a hexadecimal number, to indicate the

internal register accessed with subaddress XX of

C, and in ban 2.

The register 0x00~0x0F are common for all banks, and the bank switching using as following:

bank 0 – reg05[3][0] = ‘0’ ‘0’

bank 1 – reg05[3][0] = ‘0’ ‘1’

bank 2 – reg05[3][0] = ‘1’ ‘0’

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -4- 2013/11/12

Chap 2 IT6506 Initial

IT6506 initial can be separated into two parts. The first part is to reset the physical layer of

IT6506. The second part is to reset the logical part of IT6506.

Initial Register Setting

The following table is the setting sequence for each step. The Bit Mask means the bit to

update on each step, and the Bit Value means the updating part of each step.

Reg

Bit Mas

Bit Value

0xEA

0xFF

0xEA

0xFF

0x1

0xEB

0xFE

0x1B3

0xFE

0x1B3

0xFE

0x00

0x1B2

0xFF

0x1B2

0x0

0x1B5

0xFF

0x14

0x1B7

0xFF

0x33

0x1B8

0xFF

0x03

0x1CD

0xFF

0x80

0x1D2

0xFF

0x8

0x1D3

0xFF

0x69

0xEA

0x05

0xEA

0x05

0x04

0xEE

0x01

0x21

0xFF

0x0A

0x22

0xFF

0x64

0x2F

0xFF

0x7B

0xFD

0x05

0x31

0x40

0x32

0xFF

0xB2

0x41

0xB7

0xFF

0x10

0xB8

0xFF

0x08

0xB9

0xFF

0x10

0xBA

0xFF

0x08

0xBB

0xFF

0x30

0xBC

0xFF

0x60

0xBD

0xF0

0x00

0xC0

0xFF

0x00

0xC1

0xBF

0xB

0xC2

0xFF

0x8C

0xC3

0xFF

0x7A

0xCC

0xFF

0xC5

0xCD

0xFF

0xA8

0xE3

0x80

0xEB

0x8F

0xF

0xEC

0x26

0xEF

0x24

0xF1

0x40

0xFC

0xFF

0x21

0xD2

0xFF

0xE0

0xF6

0xFF

0x4C

0x1A5

0xFF

0xC8

0x1A2

0x10

0x00

0x1B1

0x04

0x1B1

0x78

0x00

0x170

0x0C

0x04

0xE4

0xFF

x00

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -5- 2013/11/12

0xE6

0xFF

0x00

0xE9

0xFF

0x00

0xE5

0xFF

0x07

0xE7

0xFF

0xE8

0xFF

0xC9

0x09

0xED

0xC0

0x80

0xEE

0x02

0x00

0xEE

0xFC

0xC9

0x10

0xF7

0x01

0x00

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -6- 2013/11/12

Chap 3 Event of IT6506

The events of IT6506 will activate the bits in reg06, where each bit corresponded to a group of

event shows in the table reg07~reg0C.

Reg

Name

Bit

Descrioption

Type

Reserved

7:6

------------------------------------------

IntGroup5

Group Reg0Ch Int

IntGroup4

Group Reg0Bh Int

IntGroup3

Grou

p Reg0Ah Int

IntGroup2

Group Reg09h Int

IntGroup1

Group Reg08h Int

IntGroup0

Group Reg07h Int

The event of IT6506 shows on the register Reg07~Reg0C, as the following table, where write

to one will clear the bits.

Reg

Name

Bit

Descr

ioption

Type

LSVBIDInt

VBID majority error interrupt

W1C

LSNAudInt

NAud majority error interrupt

W1C

LSMAudInt

ud majority error interrupt

W1C

LSMVidInt

Mvid majority error interrupt

W1C

RegAFUflow

udio fifo under flow

RegAFOf

low

udio fifo over flow

RegVFUflow

video fifo under flow

RegVFOflow

video fifo over flow

LSAudMuteEnd

Audio mute end interrupt

W1C

LSAudMuteStart

Audio mute start

interrupt

W1C

LSVidMuteEnd

Video mute end interrupt

W1C

SVidMuteStart

Video mute start interrupt

W1C

AutoAudMute

rite 1 will gen

REGHWMuteAACClr

W1C

RefAuxURLen

AUX receive un

support length interrupt

W1C

RefAuxURCmd

AUX receive un

support command interrupt

W1C

RefAuxSynErr

AUX receive sync l

ength error interrupt

W1C

LSNoSPDInfo

No SPD InfoFrame interrupt

W1C

LSNoMpegInfo

No Mpeg InfoFrame interrupt

W1C

LSNoAudInfo

No Audio InfoFrame interrupt

W1C

LSNoAVIInfo

No AVI InfoFrame interrupt

W1C

LSL3ECCInt

Lane 3 (2 nibble erro

r) ECC interrupt

W1C

LSL2ECCInt

Lane 2 (2 nibble error) ECC interrupt

W1C

LSL1ECCInt

Lane 1 (2 nibble error) ECC interrupt

W1C

LSL0ECCInt

Lane 0 (2 nibble error) ECC interrupt

W1C

RefL3SymUnL IRQ

Lane 3 Symbol lose loc interrupt

W1C

fL2SymUnL IRQ

Lane 2 Symbol lose loc interrupt

W1C

RefL

SymUnL IRQ

Lane 1 Symbol lose loc

interrupt

W1C

RefL

SymUnL IRQ

Lane 0 Symbol lose loc interrupt

W1C

RefLn TrnFalIRQ

Lin Training fail interrupt

W1C

RefSymUnAlgnIRQ

Symbol lose a

lignment interrupt

W1C

RefLn TrnDnIRQ

Lin Training done interrupt

W1C

RefLn TrnStrIRQ

Lin Training start interrupt

W1C

RefAuthDnIRQ

Authentication done interrupt

W1C

RefAuthStartIRQ

Authentication start interrupt

W1C

RefLCFailIRQ

n Integrity Chec fail interrupt

W1C

RefRiRdyIRQ

R0 ready interrupt

W1C

RefA svFailIRQ

Illegal A sv interrrupt

W1C

RefHPDRstNIRQ

HPD Reset interrupt

W1C

RefD3EntryInt

DPCD 00600h[1:0] have been changed to 10

from other values

W1C

RefD0En

tryInt

DPCD 00600h[1:0] have been changed to 01

from other values

W1C

Reserved

------------------------------------------

IT6506 PROGRAMMING GUIDE

ITE Tech. INC. -7- 2013/11/12

LSNewGenP t

New Mpeg InfoFrame interrupt

W1C

LSNewSPDInfo

New SPD InfoFrame interrupt

W1C

LSNewMpegInfo

New Mpe

g InfoFrame interrupt

W1C

LSNewAudInfo

New Audio InfoFrame interrupt

W1C

LSNewAVIInfo

New AVI InfoFrame interrupt

W1C

LSNewVidFormat

New Video format interrupt

W1C

RefI2CHangInt

I2C may hanging ( stay the same state too

long )

W1C

LSL32

NibbleErr

Lane 3 ECC 2 nibble error

W1C

LSL22NibbleErr

Lane 2 ECC 2 nibble error

W1C

LSL12NibbleErr

Lane 1 ECC 2 nibble error

W1C

LSL02NibbleErr

Lane 0 ECC 2 nibble error

W1C

LSL31NibbleErr

Lane 3 ECC 1 nibble error

W1C

LSL21NibbleErr

Lane 2 ECC 1 nibble error

W1C

LSL11NibbleErr

Lane 1 ECC 1 nibble error

W1C

LSL01NibbleErr

Lane 0 ECC 1 nibble error

W1C

Where interrupt mask is in RegE4~RegE9, and the bits are one-to-one mapping to

reg07~reg0C:

Reg

Name

Bit

Description

Type

Defa

ult

Value

RegIntMas

[7:0]

7:0

Interrupt Mas [7:0]

For register 07 ( one to one mapping )

R/W

11111111

RegIntMas

[15:8]

7:0

Interrupt Mas [15:8]

For register 08

R/W

11111111

RegIntMas

[23:16]

7:0

Interrupt Mas [23:16]

For Register 09

R/W

1111

RegIntMas

[31:24]

7:0

Interrupt Mas [31:24]

For Register 0A

R/W

11111111

RegIntMas

[39:32]

7:0

Interrupt Mas [39:32]

For Register 0B

R/W

11111111

RegIntMas [47]

Reserved For

future

use

R/W

RegIntMas [46:40]

6:0

For Resister 0C[6:0]

R/W

1111111

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