Lauterbach C5000 Debugger Manuale utente

MANUAL

Release 02.2022

C5000 Debugger

C5000 Debugger | 2

C5000 Debugger

TRACE32 Online Help

TRACE32 Directory

TRACE32 Index

TRACE32 Documents ...................................................................................................................... 

ICD In-Circuit Debugger ................................................................................................................ 

Processor Architecture Manuals .............................................................................................. 

TI DSPs ..................................................................................................................................... 

C5000 Debugger ................................................................................................................... 1

Brief Overview of Documents for New Users ................................................................. 5

Converter from GEL to PRACTICE .................................................................................. 5

Warning .............................................................................................................................. 6

DSP specific Implementations ......................................................................................... 7

Trigger 7

Breakpoints 7

Software Breakpoints 7

On-chip Breakpoints for Instructions 7

On-chip Breakpoints for Data 7

Memory Classes 8

DSP specific SYStem Commands ...................................................................................9

SYStem.Option.IMASKASM Disable interrupts while single stepping 9

SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 9

SYStem.CPU Select the used CPU 9

SYStem.JtagClock Define JTAG frequency 10

SYStem.MemAccess Run-time memory access 11

SYStem.Mode Establish the communication with the target 12

SYStem.CONFIG.state Display target configuration 13

SYStem.CONFIG Configure debugger according to target topology 15

<parameters> describing the “DebugPort” 20

<parameters> describing the “JTAG” scan chain and signal behavior 23

<parameters> describing a system level TAP “MultiTap” 27

<parameters> configuring a CoreSight Debug Access Port “AP” 29

<parameters> describing debug and trace “Components” 35

<parameters> which are “Deprecated” 44

SYStem.Option.AHBHPROT Select AHB-AP HPROT bits 48

SYStem.Option.AXIACEEnable ACE enable flag of the AXI-AP 48

SYStem.Option.AXICACHEFLAGS Configure AXI-AP cache bits 48

C5000 Debugger | 3

SYStem.Option.AXIHPROT Select AXI-AP HPROT bits 49

SYStem.Option.ByteMode Define byte mode 49

SYStem.Option.DAPDBGPWRUPREQ Force debug power in DAP 49

SYStem.Option.DAPSYSPWRUPREQ Force system power in DAP 50

SYStem.Option.DAPREMAP Rearrange DAP memory map 51

SYStem.Option.DEBUGPORTOptions Options for debug port handling 51

SYStem.Option.DAPNOIRCHECK No DAP instruction register check 52

SYStem.Option.DUALPORT Implicitly use run-time memory access 53

SYStem.Option.EnReset Allow the debugger to drive nRESET (nSRST) 53

SYStem.LOCK Tristate the JTAG port 53

SYStem.Option.EnTRST Control TAP reset 54

SYStem.Option.INTDIS Disable all interrupts 54

SYStem.Option.MUHP High-priority memory access 54

SYStem.Option.OVERLAY Enable overlay support 55

SYStem.Option.PWRDWN Allow power-down mode 55

SYStem.Option.TargetServer Use target server from TI 56

SYStem.Option.TURBO Use DMA for write accesses 56

SYStem.RESetOut Reset the DSP 56

SYStem.Option.CToolsDecoder Use TI’s trace decoder software 57

SYStem.Option.CtoolsNoSync CToolsNoSync 57

CPU specific BenchMarkCounter Commands ................................................................ 58

BMC.<counter>.ATOB Advise counter to count within AB-range 58

BMC.<counter>.EVENT Assign event to counter 59

TrOnchip Commands ........................................................................................................ 60

TrOnchip.state Display on-chip trigger window 60

TrOnchip.CONVert Adjust range breakpoint in on-chip resource 60

C55X specific TrOnchip Commands ............................................................................... 61

TrOnchip.ATOB Activate on-chip breakpoints in AB-range 61

TrOnchip.BMCTR Configure the benchmark counter 61

TrOnchip.CLOCK Set the clock for the benchmark counter 65

TrOnchip.CoefficientAccess AET trigger optimization 65

TrOnchip.DualAccess AET trigger optimization 65

TrOnchip.PROfile Display the benchmark data 65

TrOnchip.RESet Set on-chip trigger to default state 66

Tracing ............................................................................................................................... 67

Controlling the Trace Capture 67

Trace Breakpoints 67

JTAG Connection .............................................................................................................. 68

Mechanical Description of the 20-pin Debug Cable 68

Electrical Description of the 20-pin Debug Cable 69

Mechanical Description of the 14-pin Debug Cable 70

Electrical Description of the 14-pin Debug Cable 70

C5000 Debugger | 4

Mechanical Description of the TI Connector 71

FAQ ..................................................................................................................................... 71

Operation Voltage ............................................................................................................. 72

C5000 Debugger | 5

C5000 Debugger

Version 09-Mar-2022

Brief Overview of Documents for New Users

Architecture-independent information:

•“Training - Debugger Basics” (training_debugger.pdf): Get familiar with the basic features of a

TRACE32 debugger.

•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.

•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.

Architecture-specific information:

•“Processor Architecture Manuals”: These manuals describe commands that are specific for the

processor architecture supported by your debug cable. To access the manual for your processor

architecture, proceed as follows:

- Choose Help menu > Processor Architecture Manual.

•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating

system-aware debugging. The appropriate OS Awareness manual informs you how to enable the

OS-aware debugging.

Converter from GEL to PRACTICE

The General Extension Language (GEL) is an interpretive language similar to C that lets you create

functions to extend Code Composer Studio’s usefulness. The converter allows you to convert GEL language

into PRACTICE scripts (*.cmm), which can be used directly in TRACE32.

For more detailed information on that converter please refer to “Converter from GEL to PRACTICE”

(converter_gel.pdf).

C5000 Debugger | 6

Warning

WARNING: To prevent debugger and target from damage it is recommended to connect or

disconnect the Debug Cable only while the target power is OFF.

Recommendation for the software start:

1. Disconnect the Debug Cable from the target while the target power is

off.

2. Connect the host system, the TRACE32 hardware and the Debug

Cable.

3. Power ON the TRACE32 hardware.

4. Start the TRACE32 software to load the debugger firmware.

5. Connect the Debug Cable to the target.

6. Switch the target power ON.

7. Configure your debugger e.g. via a start-up script.

Power down:

1. Switch off the target power.

2. Disconnect the Debug Cable from the target.

3. Close the TRACE32 software.

4. Power OFF the TRACE32 hardware.

C5000 Debugger | 7

DSP specific Implementations

Trigger

A bidirectional trigger system allows the following two events:

• Trigger an external system (e.g. logic analyzer) if the program execution is stopped.

• Stop the program execution if an external trigger is asserted.

For more information refer to the TrBus command.

Breakpoints

Software Breakpoints

If a software breakpoint is used, the original code at the breakpoint location is temporarily patched by a

breakpoint code. There is no restriction in the number of software breakpoints.

On-chip Breakpoints for Instructions

If on-chip breakpoints are used, the resources to set the breakpoints are provided by the CPU. Those CPU

resources only allow to set single address instruction breakpoints.

On-chip Breakpoints for Data

To stop the CPU after a read or write access to a memory location on-chip breakpoints are required. In the

DSP notation these breakpoints are called watch points (WP).

Overview

•On-chip breakpoints: Total amount of available on-chip breakpoints.

•Instruction breakpoints: Number of on-chip breakpoints that can be used to set program

breakpoints into ROM/FLASH/EPROM.

•Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write

breakpoints.

•Data Value breakpoint: Number of on-chip data breakpoints that can be used to stop the

program when a specific data value is written to an address or when a specific data value is read

from an address.

C5000 Debugger | 8

Memory Classes

The following DSP specific memory classes are available.

To access a memory class, write the class in front of the address.

Example:

Core

On-chip

breakpoints

Instruction

breakpoints

Read/Write

breakpoint

Data Value

breakpoints

C54x 2 2 single address — —

C55x 4 up to 4 single

address

up to 3 data,

1 breakpoint

range and 2 bit

masks

up to 3

Memory Class Description

P Program Memory

D Data Memory

IO Input/Output Area

VM Virtual Memory (memory on the debug system)

E Emulation Memory, Pseudo Dualport Access to Memory

(see SYStem.CpuAccess)

Data.dump IO:0- -3

C5000 Debugger | 9

DSP specific SYStem Commands

SYStem.Option.IMASKASM Disable interrupts while single stepping

Default: OFF.

Interrupts are disabled during an assembler single-step operations, if this option is "ON".

SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping

Default: OFF.

Interrupts are disabled during HLL single-step operations, if this option is "ON".

SYStem.CPU Select the used CPU

Default selection: C55XX. Selects the processor type. If your ASIC is not listed, select the type of the

integrated DSP core.

Format: SYStem.Option.IMASKASM [ON | OFF]

Format: SYStem.Option.IMASKHLL [ON | OFF]

Format: SYStem.CPU <cpu>

C5000 Debugger | 10

SYStem.JtagClock Define JTAG frequency

Default frequency: 10 MHz.

Selects the JTAG port frequency (TCK) used by the debugger to communicate with the processor. The

frequency affects e.g. the download speed. It could be required to reduce the JTAG frequency if there are

buffers, additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency

will not work on all systems and will result in an erroneous data transfer. Therefore we recommend to use

the default setting if possible.

Format: SYStem.JtagClock [<frequency> | RTCK | RTCK <frequency>] |

ARTCK <frequency>]

<frequency>:10000. … 80000000.

<frequency> The debugger cannot select all frequencies accurately. It chooses the

next possible frequency and displays the real value in the "System

Settings" window.

Besides a decimal number like "100000." short forms like "10kHz" or

"15MHz" can also be used. The short forms imply a decimal value,

although no"." is used.

RTCK The JTAG clock is controlled by the RTCK signal (Returned TCK).

On some processor derivatives including an ARM core (e.g. OMAP)

there is the need to synchronize the processor clock and the JTAG clock.

In this case RTCK shall be selected. Synchronization is maintained,

because the debugger does not progress to the next TCK edge until after

an RTCK edge is received.

When RTCK is selected, the maximum reachable frequency is limited to

10 MHz. This limit can be changed by adding the frequency parameter. A

limitation is required that the JTAG clock speed can not become higher

than the physical interface can manage.

Example: SYStem.JtagClock RTCK 20MHz

ARTCK Accelerated method to control the JTAG clock by the RTCK signal

(Accelerated Returned TCK).

RTCK mode allows theoretical frequencies up to 1/6 of the processor

clock. For designs using a very low processor clock we offer a different

mode (ARTCK) which does not work as recommended by ARM and

might not work on all target systems. In ARTCK mode the debugger uses

a fixed JTAG frequency for TCK, independent of the RTCK signal. This

frequency must be specified by the user and has to be below 1/2 of the

processor clock speed. The signal RTCK clocks TDI and TMS and

controls the sampling of TDO.

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