Linear Technology LTC4260 Manuale utente

LTC4260

4260fc

For more information www.linear.com/LTC4260

Typical applicaTion

FeaTures DescripTion

Positive High Voltage

Hot Swap Controller with

I2C Compatible Monitoring

The LT C

4260 Hot Swap™ controller allows a board to be

safely inserted and removed from a live backplane. Using

an external N-channel pass transistor, the board supply

voltage can be ramped up at an adjustable rate. An I2C

interface and onboard ADC allow monitoring of board

current, voltage and fault status.

The device features adjustable analog foldback current

limit with latch off or automatic restart after the LTC4260

remains in current limit beyond an adjustable time-out

delay.

The controller has additional features to interrupt the host

when a fault has occurred, notify when output power is

good, detect insertion of a load card and power-up in

either the on or off state.

applicaTions

nAllows Safe Board Insertion into Live Backplane

n8-Bit ADC Monitors Current and Voltage

nI2C™/SMBus Interface

nWide Operating Voltage Range: 8.5V to 80V

nHigh Side Drive for External N-Channel MOSFET

nInput Overvoltage/Undervoltage Protection

nOptional Latchoff or Autoretry After Faults

nAlerts Host After Faults

nFoldback Current Limiting

nAvailable in 24-Lead SO, 24-Lead Narrow

SSOP and 32-Lead (5mm ×5mm) QFN Packages

nElectronic Circuit Breakers

nLive Board Insertion

nComputers, Servers

L, LT , LT C , LT M , Burst Mode, Linear Technology and the Linear logo are registered trademarks

and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Power Up Waveforms3A, 48V Card Resident Application

BACKPLANE PLUG-IN

CARD

2.67k

1.74k

49.9k

48V

SDA

SCL

ALERT

GND

VDD SENSE

LTC4260

INTVCC

100k

FDB3632

0.010Ω

10Ω

6.8nF

CL43.5k

3.57k

VOUT

48V

24k

68nF

*DIODES INC. SMBT70A

0.1µF

GATE

TIMER GND

BD_PRST

ADIN

GPIO

4260 TA01

SOURCE

SDAO

SDAI

SCL

ALERT

CONNECTOR 1

CONNECTOR 2

VIN

50V/DIV

VOUT

50V/DIV

GPIO

5V/DIV

25ms/DIV 4260 TA02

IIN

2A/DIV

CL= 1000F

LTC4260

4260fc

For more information www.linear.com/LTC4260

pin conFiguraTion

absoluTe MaxiMuM raTings

(Notes 1, 2)

TOP VIEW

GN PACKAGE

24-LEAD PLASTIC SSOP

SENSE

VDD

GND

SCL

SDAI

SDAO

ALERT

TIMER

GATE

SOURCE

GPIO

INTVCC

ADR2

ADR1

ADR0

BD_PRST

ADIN

TJMAX = 125°C, θJA = 85°C/W

TOP VIEW

SW PACKAGE

24-LEAD PLASTIC SO

SENSE

VDD

GND

SCL

SDAI

SDAO

ALERT

TIMER

GATE

SOURCE

GPIO

INTVCC

ADR2

ADR1

ADR0

BD_PRST

ADIN

TJMAX = 125°C, θJA = 75°C/W

32 31 30 29 28 27 26 25

9 10 11 12

TOP VIEW

UH PACKAGE

32-LEAD (5mm ×5mm) PLASTIC QFN

13 14 15 16

1NC

GND

SCL

GPIO

INTVCC

ADR2

VDD

VDDK

SENSE

GATE

SOURCE

SDAI

SDAO

ALERT

TIMER

ADIN

BD_PRST

ADR0

ADR1

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN 33) PCB ELECTRICAL CONNECTION OPTIONAL

ALERT, SDAO............................................ –0.3V to 6.5V

Supply Voltage (INTVCC).......................... –0.3V to 6.2V

Operating Temperature Range

LTC4260C ................................................ 0°C to 70°C

LTC4260I.............................................. –40°C to 85°C

Storage Temperature Range

GN, SW Packages..............................– 65°C to 150°C

UH Package ....................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

GN, SW Packages Only..................................... 300°C

Supply Voltages (VDD).............................– 0.3V to 100V

Input Voltages

SENSE ..............................VDD – 10V or –0.3V to VDD

SOURCE............................ GATE – 5V to GATE + 0.3V

BD_PRST, FB, ON, OV, UV...................... –0.3V to 12V

ADR0-ADR2, TIMER, ADIN........–0.3V to INTVCC + 0.3V

SCL, SDAI............................................ –0.3V to 6.5V

Output Voltages

GPIO .................................................... –0.3V to 100V

GATE (Note 3) ..................................... –0.3V to 100V

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4260CGN#PBF LTC4260CGN#TRPBF LTC4260CGN 24-Lead Plastic SSOP 0°C to 70°C

LTC4260IGN#PBF LTC4260IGN#TRPBF LTC4260IGN 24-Lead Plastic SSOP –40°C to 85°C

LTC4260CSW#PBF LTC4260CSW#TRPBF LTC4260CSW 24-Lead Plastic SO 0°C to 70°C

LTC4260ISW#PBF LTC4260ISW#TRPBF LTC4260ISW 24-Lead Plastic SO –40°C to 85°C

LTC4260CUH#PBF LTC4260CUH#TRPBF 4260 32-Lead (5mm ×5mm) Plastic QFN 0°C to 70°C

LTC4260IUH#PBF LTC4260IUH#TRPBF 4260 32-Lead (5mm ×5mm) Plastic QFN –40°C to 85°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4260

4260fc

For more information www.linear.com/LTC4260

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

General

VDD Input Supply Range l8.5 80 V

IDD Input Supply Current l2 5 mA

VDD(UVL) VDD Supply Undervoltage Lockout VDD Falling l7 7.45 7.9 V

INTVCC(UVL) VCC Supply Undervoltage Lockout INTVCC Falling l3.4 3.8 4.2 V

INTVCC Internal Regulator Voltage l5 5.5 6 V

Gate Drive

tDTurn-On Delay l50 100 150 ms

ΔVGATE External N-Channel Gate Drive

(VGATE – VSOURCE)

VDD = 20V to 80V

VDD = 8.5V to 20V

4.5

IGATE(UP) External N-Channel Pull-Up Current Gate Drive On, VGATE = 0V l–14 –18 –22 µA

IGATE(FST) External N-Channel Fast Pull-Down Fast Turn Off, VGATE = 48V, VSOURCE = 43V l300 600 1000 mA

IGATE(DN) External N-Channel Pull-Down Current Gate Drive Off, VGATE = 58V, VSOURCE = 48V l0.7 1 1.4 mA

ISOURCE SOURCE Pin Input Current SOURCE = 48V l200 400 600 µA

Input Pins

VON(TH) ON Pin Threshold Voltage VON Rising l1.19 1.235 1.27 V

ΔVON(HYST) ON Pin Hysteresis l60 130 200 mV

ION(IN) ON Pin Input Current VON = 1.2V l0 ±1 µA

VOV(TH) OV Pin Threshold Voltage VOV Rising l3.43 3.5 3.56 V

ΔVOV(HYST) OV Pin Hysteresis l70 90 120 mV

IOV(IN) OV Pin Input Current VOV = 3.5V l0 ±1 µA

VUV(TH) UV Pin Threshold Voltage VUV Rising l3.43 3.5 3.56 V

ΔVUV(HYST) UV Pin Hysteresis l310 380 440 mV

IUV(IN) UV Pin Input Current VUV = 3.5V l0 ±2 µA

VUV(RTH)UV Pin Reset Threshold Voltage VUV Falling l1.18 1.235 1.27 V

ΔVUV(RHYST) UV Pin Reset Threshold Hysteresis l80 160 250 mV

ΔVSENSE(TH) Current Limit Sense Voltage Threshold

(VDD – VSENSE)

VFB = 3.5V

VFB = 0V

ISENSE(IN) SENSE Pin Input Current VSENSE = 48V l70 100 130 µA

VFB Foldback Pin Power Good Threshold FB Rising l3.43 3.5 3.56 V

ΔVFB(HYST) FB Pin Power Good Hysteresis l80 100 120 mV

IFB Foldback Pin Input Current FB = 3.5V l0 ±2 µA

VBD_PRST(TH) BD_PRST Input Threshold VBD_PRST Rising l1.2 1.235 1.27 V

ΔVBD_PRST(HYST) BD_PRST Hysteresis l70 130 190 mV

IBD_PRST BD_PRST Pullup Current BD_PRST = 0V l–7 –10 –16 µA

VGPIO(TH) GPIO Pin Input Threshold VGPIO Rising l1.6 1.8 2 V

ΔVGPIO(HYST) GPIO Pin Hysteresis 80 mV

VGPIO(OL) GPIO Pin Output Low Voltage IGPIO = 2mA l0.25 0.5 V

IGPIO(IN) GPIO Pin Input Leakage Current VGPIO = 80V l0 ±10 µA

RADIN ADIN Pin Input Resistance VADIN = 1.28V l2 10 MΩ

IADIN ADIN Pin Input Current VADIN = 2.56V l0 ±1 µA

The ldenotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA= 25°C. VDD = 48V, unless otherwise noted.

LTC4260

4260fc

For more information www.linear.com/LTC4260

elecTrical characTerisTics

The ldenotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA= 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Timer

VTIMER(H) TIMER Pin High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l0.1 0.2 0.3 V

ITIMER(UP) TIMER Pin Pull-Up Current VTIMER = 0V l–80 –100 –120 µA

ITIMER(DN) TIMER Pin Pull-Down Current VTIMER = 1.3V l1.4 2 2.6 µA

ITIMER(RATIO) TIMER Pin Current Ratio

ITIMER(DN)/ITIMER(UP)

l1.6 2 2.7 %

AC Parameters

tPLH(GATE) Input High (ON) to GATE High

Propagation Delay

CGATE = 1pF l1 3 µs

tPHL(GATE) Input High (OV, BD_PRST), Input Low

(ON, UV) to GATE Low Propagation Delay

CGATE = 1pF l0.5 3 µs

tPHL(SENSE) (VDD – SENSE) High to GATE Low VDD – SENSE = 200mV, CGATE = 10nF l0.4 1 µs

ADC

Resolution (No Missing Codes) (Note 4) l8 Bits

Integral Nonlinearity VDD – SENSE (Note 5)

SOURCE

ADIN

±0.5

±2

±1.25

LSB

Offset Error VDD – SENSE

SOURCE

ADIN

±1.5

±1

LSB

Full Scale Error (Note 6) l±5 LSB

Total Unadjusted Error (Note 6) l±5 LSB

Full Scale Voltage (Code 255) VDD – SENSE (Note 6)

SOURCE

ADIN

100

2.50

76.5

102

2.55

104

2.60

Conversion Rate 10 Hz

I2C Interface

VADR(H) ADR0 to ADR2 Input High Voltage

Threshold

INTVCC

–0.6

INTVCC

–0.45

INTVCC

–0.25

VADR(L) ADR0 to ADR2 Input Low Voltage

Threshold

0.25 0.45 0.65 V

IADR(IN) ADR0 to ADR2 Input Current ADR0 to ADR2 = 0V, 5.5V l–80 80 µA

VSDAI,SCL(TH) SDAI, SCL Input Threshold l1.6 1.8 2 V

ISDAI,SCL(IN) SDAI, SCL Input Current SCL, SDAI = 5V l0 ±1 µA

VSDAO(OL) SDAO Output Low Voltage ISDAO = 5mA l0.2 0.4 V

VALERT(OL) ALERT Output Low Voltage IALERT = 5mA l0.2 0.4 V

ISDAO,ALERT(IN) SDAO, ALERT Input Current SDAO, ALERT = 5V l0 ±1 µA

LTC4260

4260fc

For more information www.linear.com/LTC4260

elecTrical characTerisTics

The ldenotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA= 25°C. VDD = 48V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I2C Interface Timing (Note 4)

fSCL(MAX) Maximum SCL Clock Frequency Operates with fSCL ≤ fSCL(MAX) 400 kHz

tBUF(MIN) Minimum Bus Free Time Between

Stop/Start Condition

0.12 1.3 µs

tSU,STA(MIN) Minimum Repeated Start Condition

Set-Up Time

30 600 ns

tHD,STA(MIN) Minimum Hold Time After (Repeated)

Start Condition

140 600 ns

tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns

tSU,DAT(MIN) Minimum Data Set-Up Time Input 30 100 ns

tHD,DATI(MIN) Minimum Data Hold Time Input –100 0 ns

tHD,DATO(MIN) Minimum Data Hold Time Output 300 500 900 ns

tSP(MAX) Maximum Suppressed Spike Pulse Width 50 110 250 ns

CXSCL, SDA Input Capacitance SDAI Tied to SDAO 5 10 pF

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

specified.

Note 3:

Limits on maximum rating is defined as whichever limit occurs first.

An internal clamp limits the GATE pin to a minimum of 10V above source.

Driving this pin to voltages beyond the clamp may damage the device.

Note 4: Guaranteed by design and not subject to test.

Note 5: Integral nonlinearity is defined as the deviation of a code from a

precise analog input voltage. Maximum specifications are limited by the

LSB step size and the single shot measurement. Typical specifications are

measured from the 1/4, 1/2 and 3/4 areas of the quantization band.

Note 6: For the VDD-SENSE channel, full-scale is at code 255 but codes

above 200 may be discarded by offset cancellation. Full scale error and

total unadjusted error are evaluated over the 0-200 code range. Full scale

voltage corresponds to the theoretical code 255, and is extrapolated from

a code 200 measurement.

LTC4260

4260fc

For more information www.linear.com/LTC4260

Typical perForMance characTerisTics

TA= 25°C, VDD = 48V unless otherwise noted.

IDD vs VDD

UV Low-High Threshold

vs Temperature

UV Hysteresis vs Temperature

ON, BD�PRST Low-High

Threshold vs Temperature

ON, BD�PRST Hysteresis

vs Temperature

INTVCC vs ILOAD

Current Limit Sense Voltage

vs FB Voltage

Current Limit Propagation Delay

vs Sense Voltage

TIMER Pull-Up Current

vs Temperature

VDD (V)

IDD (mA)

2.0

85°C 25°C

2.5

4260 G01

1.5

1.0 20 40 60 100

3.0

–40°C

TEMPERATURE (°C)

–50

3.46

UV LOW-HIGH THRESHOLD (V)

3.48

3.50

3.52

3.54

–25 0 25 50

4260 G02

75 100

TEMPERATURE (°C)

–50

0.34

UV HYSTERESIS (V)

0.35

0.36

0.37

0.38

0.39

–25 0 25 50

4260 G03

75 100

TEMPERATURE (°C)

–50

1.220

ON, BD_PRST LOW-HIGH THRESHOLD (V)

1.225

1.230

1.235

1.240

1.245

–25 0 25 50

4260 G04

75 100

TEMPERATURE (°C)

–50

0.10

ON, BD_PRST HYSTERESIS (V)

0.11

0.12

0.13

0.14

0.16

–25 0 25 50

4260 G05

75 100

0.15

TEMPERATURE (°C)

–50

–90

TIMER PULL-UP CURRENT (µA)

–95

–100

–105

–110

–25 0 25 50

4260 G06

75 100

FB VOLTAGE (V)

CURRENT LIMIT SENSE VOLTAGE (V

– V

SENSE

) (mV)

1 2 34

4260 G07

0.5 1.5 2.5 3.5

CURRENT LIMIT SENSE VOLTAGE (VDD – VSENSE) (mV)

0.1

CURRENT LIMIT PROPAGATION DELAY (µs)

100

1000

50 100 150 200

4260 G08

250 300 350

ILOAD (mA)

0 –2 –4 –6 –8 –10

INTV

(V)

4260 G18

6VDD = 48V

VDD = 12V

MAX ILOAD = 4.5 mA

CAUTION: DRAWING CURRENT

FROM INTVCC INCREASES POWER

DISSIPATION AND TJ

LTC4260

4260fc

For more information www.linear.com/LTC4260

Typical perForMance characTerisTics

TA= 25°C, VDD = 48V unless otherwise noted.

IGATE Pull Up vs Temperature Gate Drive vs IGATE

Gate Drive vs Temperature

Gate Drive vs VDD

ADC Total Unadjusted Error

vs Code (ADIN Pin)

GPIO VOUT Low vs IGPIO

ADC INL vs Code (ADIN Pin) ADC DNL vs Code (ADIN Pin)

ADC Full-Scale Error

vs Temperature (ADIN Pin)

TEMPERATURE (°C)

–50

–10

GATE

PULL UP (µA)

–15

–20

–25

–25 0 25 50

4260 G09

75 100

IGATE (µA)

GATE DRIVE (V

GATE

– V

SOURCE

) (V)

–20

4260 G10

0–5 –10 –15

VDD = 80V

VDD = 48V

VDD = 12V

VDD (V)

GATE DRIVE (VGATE – VSOURCE) (V)

20 30

4260 G11

10 15 25 35

85°C

25°C

–40°C

TEMPERATURE (°C)

–50

GATE DRIVE (V

GATE

– V

SOURCE

) (V)

–25 0 25 50

4260 G12

75 100

CODE

ADC TOTAL UNADJUSTED ERROR (LSB)

256

4260 G14

–1

–2 64 128 192

TEMPERATURE (°C)

–50

–2

ADC FULL-SCALE ERROR (LSB)

–1

–25 0 25 50

3708 G15

75 100

CODE

ADC INL (LSB)

0.25

256

4260 G16

–0.25

–0.50 64 128 192

0.50

CODE

ADC DNL (LSB)

0.25

256

4260 G17

–0.25

–0.50 64 128 192

0.50

IGPIO (mA)

030 50

4260 G13

10 20 40 60

GPIO VOUT LOW (V)

LTC4260

4260fc

For more information www.linear.com/LTC4260

pin FuncTions

ADIN: ADC Input. A voltage between 0V and 2.56V applied

to this pin can be measured by the onboard ADC. Tie to

ground if unused.

ADR0 to ADR2: Serial Bus Address Inputs. Tying these

pins to ground, open or INTVCC configures one of 27 pos-

sible addresses. See Table 1 in Applications Information.

ALERT:Fault Alert Output. Open-drain logic output that can

be pulled to ground when a fault occurs to alert the host

controller. A fault alert is enabled by the ALERT register.

This device is compatible with SMBus alert protocol. See

Applications Information. Tie to ground if unused.

BD_PRST: Board Present Input. Ground this pin to en-

able the N-channel FET to turn on after 100ms debounce

delay. When this pin is high, the FET is off. An internal

10µA current source pulls up this pin. Transitions on this

pin will be recorded in the FAULT register. A high-to-low

transition activates the logic to read the state of the ON

pin and clear Faults. See Applications Information.

Exposed Pad (Pin 33, UH Package): Exposed pad may

be left open or connected to device ground.

FB: Foldback and Power Good Input. A resistive divider

from the output voltage is tied to this pin. When the

voltage at this pin drops below 3.41V, the output power

is considered bad and the current limit is reduced. The

power bad condition can be indicated with the GPIO pin

and a power bad fault can be logged in this condition. See

Applications Information.

GATE: Gate Drive for External N-Channel FET. An internal

18µA current source charges the gate of the external

N-channelMOSFET. A resistor and capacitor networkfrom

this pin to ground sets the turn-on rate and compensates

the active current limit. During turn-off there is a 1mA

pull-down current. During a short circuit or undervoltage

lockout (VDD or INTVCC), a 600mA pull-down current

source between GATE and SOURCE is activated.

GND: Device Ground.

GPIO: General Purpose Input/Output. Open-drain logic

output and logic input. Defaults to pull low to indicate

power is bad. Configure according to Table 3.

INTVCC:Internal Low Voltage Supply Decoupling Output.

Connect a 0.1µF capacitor from this pin to ground. This

pin can be used to drive the other pins to logic high and

has an undervoltage lockout threshold of 3.8V.

NC: No Connect. Unconnected pins. These pins provide

extra distance between high and low voltage pins.

ON: On Control Input. A rising edge turns on the external

N-channel FET and a falling edge turns it off. This pin is

also used to configure the state of the FET ON bit (and

hence the external FET) at power up. For example if the

ON pin is tied high, then the FET ON control bit (A3) will

go high 100ms after power-up. Likewise if the ON pin is

tied low then the part will remain off after power-up until

the FET ON control bit is set high using the I2C bus. A

high-to-low transition on this pin will clear faults.

OV (GN/UH Packages): Overvoltage Comparator Input.

Connect this pin to an external resistive divider from VDD.

If the voltage at this pin rises above 3.5V, an overvoltage

fault is detected and the switch turns off. Tie to GND if

unused.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-collector output

from a master controller. An external pull-up resistor or

current source is required.

SDAI: Serial Bus Data Input. A high impedance input used

for shifting in address, command or data bits. Normally

tied to SDAO to form the SDA line.

LTC4260

4260fc

For more information www.linear.com/LTC4260

pin FuncTions

SDAO: Serial Bus Data Output. Open-drain output used for

sending data back to the master controller or acknowledg-

ing a write operation. Normally tied to SDAI to form the

SDA line. An external pull-up resistor or current source

is required.

SENSE: Current Sense Input. Connect this pin to the out-

put of the current sense resistor. The current limit circuit

controls the GATE pin to limit the sense voltage between

the VDD and SENSE pins to 50mV or less depending on

the voltage at the FB pin. This pin is used as an input to

the 8-bit ADC.

SOURCE: N-Channel MOSFET Source Connection and

ADC Input. Connect this pin to the source of the external

N-channel MOSFET switch. This pin also serves as the

ADC input to monitor output voltage. The pin provides a

return for the gate pull-down circuit and as a supply for

the charge pump circuit.

TIMER:

Timer Input. Connect a capacitor between this pin

and ground to set a 12ms/µF duration for current limit

before the switch is turned off. The duration of the off

time is 518ms/µF when autoretry during current limit is

enabled. A minimum value of 0.1nF must be connected

to this pin.

UV: Undervoltage Comparator Input. Connect this pin

to an external resistive divider from VDD. If the voltage

at this pin falls below 3.12V, an undervoltage fault is

detected and the switch turns off. Pulling this pin below

1.2V resets all faults and allows the switch to turn back

on. Tie to INTVCC if unused.

VDD:Supply Voltage and Current Sense Input. This pin

has an undervoltage lockout threshold of 7.45V.

VDDK (UH Package): Same as VDD. Connect this pin to

VDD. VDDK tied to VDD internally with 18Ω.

LTC4260

4260fc

For more information www.linear.com/LTC4260

FuncTional DiagraM

–

3.5V

UVS

OVS

RESET

ONS

VDD UVLO

3.5V

1.235V

INTVCC

1.235V

7.45V

SOURCE

I2C

VDD – SENSE

I2C ADDR

–

3.5V –

PWRGD FET ON

–

RST

–

BOARD

PRESENT

–

1.235V –

0.2V

LOGIC

TM2

UVLO2

–

UVLO1

GN/UH ONLY

BD_PRST

10µA

SDAI

SDAO

SCL

ALERT

ADR0 ADR1 ADR2 GND

UH ONLY

EXPOSED

PAD

VDD

ADIN

1 OF 27

3.8V

VCC UVLO

4260 BD

INTVCC

TIMER

GPIO

INTVCC

VDD

100µA

1.8V

2µA

A/D CONVERTER

5.5V

GEN

TM1

SOURCE

16.5V

GATE

–

VDDK

VDD

18Ω

SENSE

UH ONLY

INTERNAL

POWER CHARGE

PUMP

AND

GATE

DRIVER

FOLDBACK

20mV TO

50mV

+–

Indice

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