Microsemi IGLOO2 FPGA DSP FIR Filter Manuale utente

IGLOO2 FPGA Evaluation Kit

User Guide

IGLOO2 FPGA Evaluation Kit User Guide

IGLOO2 FPGA Evaluation Kit User Guide 3

Table of Contents

1 – Introduction .............................................................................................. 5

Kit Contents................................................................................................................................5

IGLOO2 FPGA Evaluation Kit Web Resources.........................................................................5

Board Description.......................................................................................................................5

2 – Installation and Settings ......................................................................... 9

Software Installation...................................................................................................................9

Hardware Installation .................................................................................................................9

IGLOO2 Power Sources ..........................................................................................................11

Testing the Hardware...............................................................................................................11

3 – Key Components Description and Operation ..................................... 13

Powering Up the Board............................................................................................................13

Current Measurement..............................................................................................................13

Memory Interface.....................................................................................................................15

SERDES0 Interface .................................................................................................................16

USB Interface...........................................................................................................................18

Marvell PHY (88E1340S).........................................................................................................18

Programming............................................................................................................................20

FTDI Interface..........................................................................................................................20

I2C Port Header.......................................................................................................................21

System Reset...........................................................................................................................22

Clock Oscillator........................................................................................................................22

Debugging................................................................................................................................23

GPIO Header Pin Out ..............................................................................................................25

4 – Pin List .................................................................................................... 27

5 – Board Components Placement ............................................................. 41

6 – Demo Design .......................................................................................... 45

M2GL-EVAL-KIT Board Demo Design.....................................................................................45

7 – Manufacturing Test ................................................................................ 47

M2GL-EVAL-KIT Board Testing Procedures...........................................................................47

Switches and LED Tests..........................................................................................................58

Debugging the Board...............................................................................................................58

List of Changes ............................................................................................ 60

Table of Contents

4 IGLOO2 FPGA Evaluation Kit User Guide

Product Support .......................................................................................... 61

Customer Service.....................................................................................................................61

Customer Technical Support Center........................................................................................61

Technical Support....................................................................................................................61

Website ....................................................................................................................................61

Contacting the Customer Technical Support Center ...............................................................61

ITAR Technical Support...........................................................................................................62

IGLOO2 FPGA Evaluation Kit User Guide 5

1 – Introduction

The IGLOO®2 field programmable gate array (FPGA) Evaluation Kit (M2GL-EVAL-KIT) is RoHS compliant and

enables the designer to develop applications that involve one or more of the following:

•Motor control

•System management

•Industrial automation

•High speed serial I/O applications like PCIe, SGMII, and user customizable serial interfaces

Kit Contents

Table 1 lists the contents of the IGLOO2 Evaluation Kit.

Table 1. Kit Contents

Quantity Description

1 IGLOO2 Evaluation Board with M2GL010T-1FGG484

1 FlashPro4 JTAG programmer for programming and debugging of the IGLOO2 device

1 USB 2.0 A male to mini-B Y-cable for UART/power interface (up to 1A) to PC

1 +12 V/2 A Wall-Mounted power supply

- FTDI drivers to perform the MTD test

IGLOO2 FPGA Evaluation Kit Web Resources

IGLOO2 Evaluation Kit web resources are available at:

http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/igloo2/igloo2-evaluation-kit#overview

Board Description

The IGLOO2 Evaluation Kit offers a full-featured Evaluation Board for IGLOO2 FPGAs. This kit inherently integrates

the following on a single chip:

•Reliable flash-based FPGA fabric

•Advanced security processing accelerators

•Digital signal processing (DSP) blocks

•Static random-access memory (SRAM)

•Embedded nonvolatile memory (eNVM)

•Industry-required high-performance communication interfaces

The board has numerous interfaces including an RJ45 for 10/100/1000 Ethernet, one Full-Duplex SERDES Lane

through sub miniature version A (SMA) connectors, a 64-bit GPIO Header, and various connectors for SPI support.

The IGLOO2 memory management system is supported by 512 Mb of on board mobile LPDDR SDRAM memory and

64 Mb SPI flash. The serializer and deserializer (SERDES) block can be accessed through the peripheral component

interconnect express (PCIe) edge connector or high speed SMA connectors.

•The board supports the M2GL010T device in an FG484 package

•The board is eight layers PCB and manufactured with FR4 dielectric material.

1 – Introduction

6 IGLOO2 FPGA Evaluation Kit User Guide

Block Diagram

Figure 1 shows the IGLOO2 evaluation kit block diagram:

IGLOO2 FPGA – M2GL010T-1FGG484

GPIO Header

PHY

88E1340S RJ45

PCIE edge

connector

FP4 HeaderRVI Header

ETM HeaderUSB3320

FT4232

Lane 3

Lane 0

SPI_0

Bank2

USB micro AB

connector

USB mini B

connector

Bank1

SGMII

MSIO

Bank7

SERDES0

SPI flash

W25Q64FV

SSIG

LPDDR

MT46H32M16LF

8 Meg x 16 x 4

banks

MDDR

Bank0

JTAG

Bank4 SC_SPI

ETM

Bank1

MDIO

Bank7

Debug

Switches-4 Bank2

MSIO

Bank4

MSIO

Bank1

U15

J4 J5

REFCLK0

Lane 1

Lane 2 SMA

Connectors

REFCLK1

JTAG PHY

23-pin header

Debug LEDs-8 Bank7

On Board

Oscillator-

125MHz

SMA

Connectors

Mux

Figure 1. IGLOO2 FPGA Evaluation Kit Block Diagram

Board Overview

Figure 2 shows an overview of the IGLOO2 Evaluation Kit Board features.

Figure 2. IGLOO2 FPGA Evaluation Kit Board Overview

1 – Introduction

IGLOO2 FPGA Evaluation Kit User Guide 7

I/O Voltage Rails

Table 2 lists the bank I/Os with voltage rails.

Table 2. I/O Voltage Rails

IGLOO2 Bank I/O Rail Voltage

Bank0 VDDI0 1.8 V

Bank1 VDDI1 3.3 V

Bank2 VDDI2 3.3 V

Bank3 VDDI3 3.3 V

Bank4 VDDI4 3.3 V

Bank5 VDDI5 2.5 V

Bank6 VDDI6 2.5 V

Bank7 VDDI7 3.3 V

Table 3 describes the IGLOO2 FPGA Evaluation Kit Board components.

Table 3. IGLOO2 FPGA Evaluation Kit Board Components

Name

Description

M2GL010T-1FGG484 Microsemi IGLOO2 FPGA

Mobile Low-Power DDR

SDRAM 512 Mb (MT46H32M16LF – 8 Meg x 16 x 4 banks) for storing the data bits.

SPI flash 64 Mb SPI flash Winbond electronics W25Q64FVSSIG connected to SPI port 0 of the IGLOO2

FPGA high performance memory system (HPMS).

Ethernet RJ45 connector (Ethernet jack with magnetic) interfacing with Marvell 10/100/1000 BASE-T PHY

chip 88E1340S in serial gigabit media independent interface (SGMII) mode, interfacing with the

Ethernet port of the IGLOO2 FPGA (on-chip MAC and external PHY).

RVI header RVI header for application programming and debugging from Keil ULINK or IAR J-Link.

FP4 header FlashPro4 programming header for IGLOO2 programming and debugging with Microsemi tools.

Future Technology

Devices International

(FTDI) programmer

FTDI programmer interface (J18) to program the external SPI flash.

mbedded trace macro

(ETM) cell header ETM header for debugging.

GPIO header General purpose input/output (GPIO) header for multi standard I/O (MSIO) signals to be routed.

PCIe edge connector PCI Express edge connector with one lane

Dual in-line package (DIP)

switch Debug switch for user application.

Light-emitting diodes

(LEDs) Eight active low LEDs that are connected to some of the user I/Os for debug.

Three active high LEDs that are used for power supply indication.

Push–button reset Push-button system reset for IGLOO2 system.

Push–button switches Four push-button switches for test and navigation.

USB interface

USB micro AB connector, interfacing with the high speed USB2.0 ULPI transceiver chip

1 – Introduction

8 IGLOO2 FPGA Evaluation Kit User Guide

Name Description

USB3320, interfacing with FPGA pins of the IGLOO2 HPMS.

OSC-125 125 MHz clock oscillator (differential output)

OSC-50 50 MHz clock oscillator

OSC-32 32.768 KHz low-power oscillator

IGLOO2 FPGA Evaluation Kit User Guide 9

2 – Installation and Settings

Software Installation

Download and install the latest release of Microsemi Libero®System-on-Chip (SoC) software v11.1 or later, from the

Microsemi website and register for a free Gold license. For instructions on how to install Libero and SoftConsole,

refer to the Libero Installation and Licensing Guide available on the Microsemi website.

Refer to the Installing IP Cores and Drivers User Guide to download and install Microsemi DirectCores, SGCores,

and driver firmware cores. These must be localized on the PC where Microsemi Libero is installed while designing

with Microsemi FPGAs.

Hardware Installation

The FlashPro4 programmer can be used to program the M2GL-EVAL-KIT board.

Jumpers, Switches, LEDs, and DIP Switch Settings

The recommended default jumpers, switches, LEDs, and DIP switch settings are defined in Table 4 through Table 6.

•Table 4 Jumper Settings

•Table 5 LEDs

•Table 6 Test Points

Connect the jumpers using the default settings to enable the pre-programmed demonstration design to function

correctly. Table 4 shows the jumpers along with default settings.

Note: Location of all the jumpers and test points are searchable in Figure 17 (page 42) of 5 – Board Components

Placement section.

Table 4. Jumper Settings

Jumper Function Default Settings

J23

Jumper to select switch-side Mux inputs of A or B to the line side. –

Pin 1-2 (Input A to the line side) that is on board 125 MHz differential

clock oscillator output will be routed to line side. Closed

Pin 2-3 (Input B to the line side) that is external clock required to source

through SMA connectors to the line side. Open

J22

Jumper to select the output enables control for the line side outputs. –

Pin 1-2 (Line side output enabled) Closed

Pin 2-3 (Line side output disabled) Open

J24 Jumper to provide the VBUS supply to USB when using in Host mode. Open

JTAG selection jumper to select between RVI header or FP4 header for

application debug. –

Pin 1-2 FP4 for SoftConsole/FlashPro Closed

Pin 2-3 RVI for Keil ULINK™/IAR J-Link®Open

Pin 2-4 for Toggling JTAG_SEL signal remotely using GPIO capability of

FT4232 chip. Open

J3 Jumpers to select either SW2

input or signal ENABLE_FT4232 from

FT4232H chip. –

2 – Installation and Settings

10 IGLOO2 FPGA Evaluation Kit User Guide

Jumper Function Default Settings

Pin 1-2 for Manual power switching using SW7 switch. Closed

Pin 2-3 for Remote power switch using GPIO capability of FT4232 chip. Open

Table 5 lists the power supply and Ethernet LEDs.

Table 5. LEDs

LED Comment

DS1 - Green Indicates the 5 V rail.

DS2 - Green Indicates the 3.3 V rail.

DS3 - Green Indicates the 12 V power source.

DS5 - Green Connected to parallel LED output port 0 (P0_LED[0]) of Marvell PHY.

DS4 - Green Connected to parallel LED output port 0 (P0_LED[2]) of Marvell PHY.

DS6 - Green Connected to parallel LED output port 0 (P0_LED[3]) of Marvell PHY.

Table 6 lists the USB, ground, and other test points.

Table 6. Test Points

Test Point Description

TP8 USB switch in/out for DP signal.

TP9 USB switch in/out for DM signal.

TP1, TP2, TP4, TP5, TP6, TP7, TP10,

TP11 GND

TP3 Test point for DDR_VTT

TP12 Test point to measure the voltage at TP12 with reference to GND.

TP14 1.2 V current sensing test point

TP15 1.8 V current sensing test point

TP16, TP17 Test points across current sense resistor 0.05 Ohms for 1.2 V

TP18, TP19 Test points across current sense resistor 0.05 Ohms for 1.8 V

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