NXP Semiconductors UM11653 Manuale utente
UM11653
RDGD3160I3PH5EVB Reference Design
Rev. 1 — 12 August 2021 User manual
Document information
Information Content
Keywords RDGD3160I3PH5EVB, GD3160, MPC5777C-DEVB, MPC5744P, MPC5775B/
E-EVB, S32S Design Studio SDK, FreeMASTER, AMMCL, MCAT
Abstract This document is the user guide for the RDGD3160I3PH5EVB reference
design and is intended for the engineers involved in the evaluation, design,
implementation, and validation of single-channel gate driver for IGBT,
GD3160.
NXP Semiconductors UM11653
RDGD3160I3PH5EVB Reference Design
Revision History
Rev Date Description
RDGD3160I3PH5EVB v.1 20210812 Initial version
Revision history
UM11653 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 12 August 2021
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NXP Semiconductors UM11653
RDGD3160I3PH5EVB Reference Design
Important notice
NXP provides the enclosed product(s) under the following conditions:
This reference design is intended for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed
circuit board to make it easier to access inputs, outputs, and supply terminals. This
reference design may be used with any development system or other source of I/O
signals by simply connecting it to the host MCU or computer board via off-the-shelf
cables. Final device in an application will be heavily dependent on proper printed circuit
board layout and heat sinking design as well as attention to supply filtering, transient
suppression, and I/O signal quality.
The goods provided may not be complete in terms of required design, marketing, and
or manufacturing related protective considerations, including product safety measures
typically found in the end product incorporating the goods. Due to the open construction
of the product, it is the user's responsibility to take any and all appropriate precautions
with regard to electrostatic discharge. In order to minimize risks associated with the
customers applications, adequate design and operating safeguards must be provided
by the customer to minimize inherent or procedural hazards. For any safety concerns,
contact NXP sales and technical support services.
UM11653 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 12 August 2021
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RDGD3160I3PH5EVB Reference Design
1 Introduction
This document is the user guide for the RDGD3160I3PH5EVB reference design.
This document is intended for the engineers involved in the evaluation, design,
implementation, and validation of single-channel gate driver for IGBT, GD3160.
The scope of this document is to provide the user with information to evaluate the single
channel gate driver for IGBT, GD3160. This document covers connecting the hardware,
installing the software and tools, configuring the environment and using the kit.
The RDGD3160I3PH5EVB is a fully functional three-phase inverter evaluation board
populated with six GD3160 gate drivers with fault management and supporting
circuitry. This board supports SPI daisy chain communication for programming and
communication with three high-side gate drivers and three low-side gate drivers
independently.
This board has low-voltage and high-voltage isolation in conjunction with gate drive
integrated galvanic signal isolation. Other supporting features on the board include
desaturation short-circuit detection, IGBT temperature sensing, DC Link bus voltage
monitoring, phase current sensing, and motor resolver excitation and signal processing
connection circuitry. See GD3160 data sheet for additional gate drive features.
2 Finding kit resources and information on the NXP web site
The NXP analog product development boards provide an easy-to-use platform for
evaluating NXP products. The boards support a range of analog, mixed-signal and
power solutions. They incorporate monolithic integrated circuits and system-in-package
devices that use proven high-volume technology. NXP products offer longer battery life, a
smaller form factor, reduced component counts, lower cost and improved performance in
powering state-of-the-art systems.
NXP Semiconductors provides online resources for this reference design and its
supported device(s) on http://www.nxp.com.
The information page for RDGD3160I3PH5EVB reference design is at www.nxp.com/
RDGD3160I3PH5EVB. The information page provides overview information, technical
and functional specifications, ordering information, documentation, and software.
The Get Started provides quick-reference information applicable to using the
RDGD3160I3PH5EVB reference design, including the downloadable assets.
3 Getting started
Working with the RDGD3160I3PH5EVB requires the kit contents, additional hardware,
and a Windows PC workstation with installed software.
3.1 Kit contents
•Assembled and tested RDGD3160I3PH5EVB (three-phase inverter populated with
5.0 V compatible gate driver devices) board in an anti-static bag
•Quick Start Guide
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User manual Rev. 1 — 12 August 2021
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NXP Semiconductors UM11653
RDGD3160I3PH5EVB Reference Design
3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when
working with this kit.
•Microcontroller for SPI communication
•IGBT module Infineon HP Drive part FS820R08A6P2B
•DC link capacitor compatible with IGBT part FS820R08A6P2B
•HV power supply with protection shield and hearing protection
•Current sensors for monitoring each phase current
•12 V, 1.0 A DC power supply
•High sample rate digital oscilloscope with probes
•High-voltage differential voltage probe
3.3 Windows PC workstation
This reference design requires a Windows PC workstation. Meeting these minimum
specifications should produce great results when working with this reference design.
•USB-enabled computer with Windows 7 or Windows 10
3.4 Software
Installing software is necessary to work with this reference design. All listed software
is available on the reference design's information page at http://www.nxp.com/
RDGD3160I3PH5EVB.
•S32S Design Studio IDE for power architecture
•Automotive Math and Motor Control Library (AMMCL)
•FreeMaster 2.0 runtime debugging tool
•Motor Control Application Tuning (MCAT)
•GD3160 Device Driver example code REV1.2
4 Getting to know the hardware
4.1 Kit overview
4.1.1 RDGD3160I3PH5EVB features
•Capability to connect to HP Drive IGBT modules for full three-phase evaluation and
development
•Daisy chain SPI communication (three high-side and three low-side gate drivers)
•Power supply which is jumper configurable for VEE negative or GND reference
•Easy access power, ground, and signal test points
•2 × 2 32 PCIe socket for interfacing MCU control
•Note: INTA pin is a new feature added to the GD3160. Not connected to MCU
interface. See GD3160 data sheet for pin usage/features.
•Optional connection for DC bus voltage monitoring
•Compatible with MPC5777C-DEVB, MPC5775B/E-EVB, MPC5744P
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NXP Semiconductors UM11653
RDGD3160I3PH5EVB Reference Design
4.1.2 Voltage domains, GD3160 pinout, logic header, and IGBT pinout
Low-voltage domain is an externally supplied 12 V DC (VSUP) primary supply for non-
isolated circuits, typically supplied by vehicle battery. The low-voltage domain includes
the interface between the MCU and GD3160 control registers and logic control.
Low-side driver and high-side driver domains are isolated high-voltage driver control
domains for IGBT single phase connections and control circuits. Pins on bottom of board
are designed to easily connect to three-phase IGBT module.
Figure 1. RDGD3160I3PH5EVB three-phase inverter board voltage domains and interfaces
4.2 Featured components
4.2.1 Advanced IGBT gate driver
4.2.1.1 General description
The GD3160 is an advanced single channel gate driver for IGBTs. Integrated Galvanic
isolation and low on-resistance drive transistors provide high charging and discharging
current, low dynamic saturation voltage, and rail-to-rail gate voltage control.
Current and temperature sense minimizes IGBT stress during faults. Accurate and
configurable under voltage lockout (UVLO) provides protection while ensuring sufficient
gate drive voltage headroom.
The GD3160 autonomously manages severe faults and reports faults and status via the
INTB pin and a SPI interface. It is capable of directly driving gates of most IGBTs. Self-
test, control, and protection functions are included for design of high reliability systems
(ASIL C/D). It meets the stringent requirements of automotive applications and is fully
AEC-Q100 grade 1 qualified.
4.2.1.2 GD3160 features
•Compatible with current sense and temp sense IGBTs
•Fast short circuit protection for IGBT/SiC with DESAT and current sense feedback
•Compliant with ASIL D ISO 26262 functional safety requirements
•SPI interface for safety monitoring, programmability, and flexibility
•Integrated Galvanic signal isolation
•Integrated gate drive power stage capable of 15 A peak source and sink
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User manual Rev. 1 — 12 August 2021
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RDGD3160I3PH5EVB Reference Design
•Interrupt pin for fast response to faults
•Compatible with negative gate supply
•Compatible with 200 V to 1700 V IGBTs, power range > 125 kW
•AEC-Q100 grade 1 qualified
4.2.2 GD3160 pinout and MCU interface pinout
See GD3160 advanced IGBT/SiC gate driver data sheet for specific information about
pinout, pin descriptions, specifications, and operating modes.
VSUP DC supply terminal is a low voltage input connection for supplying power to the
low voltage non-isolated die and related circuitry. Typically supplied by vehicle battery
+12 V DC.
MCU connector is a 2×32-pin PCIe interface connector for use with either MPC5744P,
MPC5775B/E-EVB or MPC5777C 32-bit MCU board or any other MCU of preference. An
MCU is needed for SPI communication and control of advanced IGBT gate drive devices
(GD3160).
Figure 2. Gate driver pinout and board interface connection PCIe 2 × 32
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RDGD3160I3PH5EVB Reference Design
Pin Name Function
A1 VDDA Voltage reference resolver circuit
A2 GNDA1 Analog ground
A3 PH_U_I Current feedback phase U
A4 PH_V_I Current feedback phase V
A5 PH_W_I Current feedback phase W
A6 n.c. not connected
A7 n.c. not connected
A8 SIN_OUT_RSLV Sine resolver signal
A9 COS_OUT_RSLV Cosine resolver signal
A10 n.c. not connected
A11 GNDA4 Analog ground
A12 n.c. not connected
A13 GND2 Ground
A14 PWMHU Pulse width modulation high-side phase U
A15 PWMLU Pulse width modulation low-side phase U
A16 PWMHV Pulse width modulation high-side phase V
A17 PWMLV Pulse width modulation low-side phase V
A18 PWMHW Pulse width modulation high-side phase W
A19 PWMLW Pulse width modulation low-side phase W
A20 n.c. not connected
A21 n.c. not connected
A22 AOUTHW Analog output signal high-side phase W
A23 n.c. not connected
A24 n.c. not connected
A25 n.c. not connected
A26 INTBHU GD3160 fault reporting pin for high-side phase U
A27 INTBLU GD3160 fault reporting pin for low-side phase U
A28 INTBHV GD3160 fault reporting pin for high-side phase V
A29 INTBLV GD3160 fault reporting pin for low-side phase V
A30 CSBH Chip select bar to high gate drive devices
A31 INTBHW GD3160 fault reporting pin for high-side phase W
A32 INTBLW GD3160 fault reporting pin for low-side phase W
B1 VREF Voltage reference from MCU
B2 GNDA2 Analog ground
B3 NC not connected
B4 DCV Optional DC bus voltage monitoring (not used by default)
B5 n.c. not connected
B6 n.c. not connected
B7 n.c. not connected
B8 SIN_N_OUT_RSLV Sine resolver signal
Table 1. PCIe connector pin definitions
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RDGD3160I3PH5EVB Reference Design
Pin Name Function
B9 COS_N_OUT_RSLV Cosine resolver signal
B10 n.c. not connected
B11 GNDA3 Analog ground
B12 MCU_VCC MCU VCC regulator voltage
B13 GND1 Ground
B14 AOUTHU GD3160 analog output signal high-side U phase
B15 AOUTLU GD3160 analog output signal low-side U phase
B16 AOUTLV GD3160 analog output signal low-side V phase
B17 AOUTHV GD3160 analog output signal high-side V phase
B18 AOUTLW GD3160 analog output signal low-side W phase
B19 RES_REF Resolver reference voltage
B20 SW_RUN Signal from onboard switch demo mode
B21 MISO_MICRO SPI slave out signal
B22 MOSI_MICRO SPI slave in signal
B23 SCLK SPI clock
B24 CSBL Chip select bar to low-side gate drivers
B25 n.c. not connected
B26 n.c. not connected
B27 n.c. not connected
B28 FSENB Fail-safe state enable bar
B29 FSSTATEL Fail-safe state low-side
B30 FSSATEH Fail-safe state high-side
B31 VSUP 12 V voltage supply (low voltage domain)
B32 GNDP Ground connection (low voltage domain)
Table 1. PCIe connector pin definitions...continued
4.2.3 Test points
All test points are clearly marked on the board. The following figure shows the location of
various test points.
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RDGD3160I3PH5EVB Reference Design
Figure 3. RDGD3160I3PH5EVB test points
Test point name Function
DCV Micro DC voltage
DSTHU DESAT high-side U phase VCE desaturation connected to DESAT pin circuitry
DSTHV DESAT high-side V phase VCE desaturation connected to DESAT pin circuitry
DSTHW DESAT high-side W phase VCE desaturation connected to DESAT pin circuitry
DSTLU DESAT low-side U phase VCE desaturation connected to DESAT pin circuitry
DSTLV DESAT low-side V phase VCE desaturation connected to DESAT pin circuitry
DSTLW DESAT low-side W phase VCE desaturation connected to DESAT pin circuitry
FSISHU Not used – for test purposes only
FSISHV Not used – for test purposes only
FSISLU Not used – for test purposes only
FSISLV Not used – for test purposes only
FSISLW Not used – for test purposes only
GHU Gate high-side U phase which is the charging pin of IGBT gate
GHV Gate high-side V phase which is the charging pin of IGBT gate
GHW Gate high-side W phase which is the charging pin of IGBT gate
GLU Gate low-side U phase which is the charging pin of IGBT gate
GLV Gate low-side V phase which is the charging pin of IGBT gate
GLW Gate low-side W phase which is the charging pin of IGBT gate
NCLU – NCHW INTA test point connections to respective gate drive devices.
INTA fault reporting and real time VGE or VCE monitoring.
Resolver circuit Test points for internal signals of resolver circuit (see schematic for more information)
SPI DBG SPI signal port for analyzing SPI signals (see schematic for signals)
TSENSEHU TSENSE high-side U phase connected to NTC temperature sense
TSENSEHV TSENSE high-side V phase connected to NTC temperature sense
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