NXP Semiconductors UM11596 Manuale utente

UM11596

PTN3944 linear equalizer application board user manual

Rev. 1 — 14 July 2021 User manual

Document information

Information Content

Keywords PTN3944, PCIe, linear redriver

Abstract UM11596 demonstrates application board capability, interfacing an PCIe

device with a host computer on a x16 slot. The application board is intended

for use as an evaluation board, customer demonstration tool, and a reference

design.

NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

Rev Date Description

1 20210714 Initial release

Revision history

User manual Rev. 1 — 14 July 2021

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

Important notice

NXP provides the enclosed product(s) under the following conditions:

This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR

EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a

printed circuit board to make it easier to access inputs, outputs, and supply terminals.

This evaluation board may be used with any development system or other source of

I/O signals by simply connecting it to the host MCU or computer board via off-the-

shelf cables. This evaluation board is not a Reference Design and is not intended to

represent a final design recommendation for any particular application. Final device in

an application will be heavily dependent on proper printed circuit board layout and heat

sinking design as well as attention to supply filtering, transient suppression, and I/O

signal quality.

The goods provided may not be complete in terms of required design, marketing, and

or manufacturing related protective considerations, including product safety measures

typically found in the end product incorporating the goods. Due to the open construction

of the product, it is the user's responsibility to take any and all appropriate precautions

with regard to electrostatic discharge. In order to minimize risks associated with the

customers applications, adequate design and operating safeguards must be provided

by the customer to minimize inherent or procedural hazards. For any safety concerns,

contact NXP sales and technical support services.

User manual Rev. 1 — 14 July 2021

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

1 Introduction

The PTN3944 is a high-performance, multi-channel, linear equalizer optimized for PCIe

4.0, UPI, and similar high-speed interfaces. Using multiple components of the PTN3944

supports redriving PCIe signals on x1, x2, x4, x8, or x16 devices installed in a PCIe slot.

This document details how to properly connect the evaluation board in a system in order

to interface a chipset and a PCIe device. The document also illustrates; the Graphical

User Interface (GUI) to configure the equalizer settings of transmitters and receivers;

LPCUSBSIO module operation; and configuration with the PTN3944 application board.

2 PTN3944 PCIe Add-In-Card

The PTN3944 PCIe Add-In-Card (AIC) is designed for use in an available PCIe x16 slot

on a PC or server computer. In addition, using the CEM connector on the top, a PCIe

device can be attached. On the front side of the AIC, there are four PTN3944 that redrive

PCIe signals from motherboard side (from CPU/chipset) to the PCIe device. On the

back side of the AIC, another 4 PTN3944 redrive PCIe signals from a PCIe device to the

motherboard side (to CPU/chipset). The PTN3944 equalizer, output swing level, or flat

gain settings can be configured through either an I2C bus, or using the onboard pull-up/

down DIP switches.

The AIC power is supplied from either gold finger 3.3 V, or from an external 5.0 V power

supply. Each redriver consumes up to 250 mA of current at 1.8 V. With all 8 components

of the PTN3944 active at the same time, the AIC consumes up to 2 A of current at 1.8 V.

NXP recommends using an external 5.0 V, 1 A power supply instead of using power

from the PCIe gold finger. An onboard DC-to-DC power converter converts 5.0 V input to

1.8 V.

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

2.1 Block diagram

aaa-042292

TX_OUT[0:3]

RX_OUT[0:3]

U1 x4x4

x4x4

TX_IN[0:3]

RX_IN[0:3]

TX_OUT[4:7]

RX_OUT[4:7] x4x4 RX_IN[4:7]

TX_IN[4:7]

x4x4 TX_OUT[8:11]

RX_OUT[8:11] x4x4 RX_IN[8:11]

TX_IN[8:11]

x4x4 TX_OUT[12:15]

RX_OUT[12:15] x4x4 RX_IN[12:15]

U11

PCA9540

U10

REG1117-3.3

I2C

TX_IN[12:15]

J13

J17

TPS62827

5 V

1.8 V

J12J11

5 V 3.3 V

3.3 V

J16

Figure 1. Block diagram

2.2 PCB photographs

Figure 2. PTN3944 PCIe add-in-card front side

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

Figure 3. PTN3944 PCIe add-in-card back side

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

2.3 PTN3944 PCIe Add-In-Card schematics

2.3.1 Front side redrivers

aaa-042295

0.22 µF

0.22 µF C10

0.22 µF

C11

0.22 µF C12

0.22 µF

C13

0.22 µF C14

0.22 µF

C15

0.22 µF C16

0.22 µF

0.22 µF 34

NC1

NC2

VDD

VCCA

VCCB

VCCC

VCCD

T1_TEST1

TX_IN3N

TX_IN3P

TX_IN2N

TX_IN2P

TX_IN1N

TX_IN1P

TX_IN0N

TX_IN0P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

IN0N

IN0P

T1_OUT3N

GND

I2C Address

010-0011 (0x23)

GND

VDD1V8

FG1_T1

FG2_T1

SCL1

SDA1

FG1_T1

FG2_T1

SCL1

SDA1

SCL

SDA

T1_OUT3P

T1_OUT2N

TX_IN0P

TX_IN0N

TX_IN1P

TX_IN1N

TX_IN2P

TX_IN2N

TX_IN3P

TX_IN3N

TX_OUT0P

TX_OUT0N

TX_OUT1P

TX_OUT1N

TX_OUT2P

TX_OUT2N

TX_OUT3P

TX_OUT3N

T1_OUT2P

T1_OUT1N

T1_OUT1P

T1_OUT0N

TX_OUT0P

OUT3N

OUT3P

ADDR3

ADDR4

ADDR2

ADDR1

FG2

FG1

OUT2N

OUT2P

OUT1N

OUT1P

OUT0N

OUT0P

CTL1_T1

CTL2_T1

CTL3_T1

T1_TEST1

PTNVCC1

CTL1_T1

CTL2_T1

CTL3_T1

TEST1

LCTL1

LCTL2

LCTL3

GND6

GND5

GND4

GND3

GND2

GND1

TEST2

GND

PESD3V3R1BSFD1

D10

D11

D12

D13

D14

D15

D16

39 38 37 31404142

PTN3944

PESD3V3R1BSF

Figure 4. Front side U1 redrivers schematic

User manual Rev. 1 — 14 July 2021

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

aaa-042296

C22

0.22 µF

C23

0.22 µF

C30

0.22 µF C31

0.22 µF

C32

0.22 µF C33

0.22 µF

C34

0.22 µF C35

0.22 µF

C36

0.22 µF

56 kΩ

C37

0.22 µF

C24

0.22 µF

C25

0.22 µF

C26

0.22 µF

C27

0.22 µF

C28

0.22 µF

C29

0.22 µF 34

NC1

NC2

VDD

VCCA

VCCB

VCCC

VCCD

T2_TEST1

TX_IN7N

TX_IN7P

TX_IN6N

TX_IN6P

TX_IN5N

TX_IN5P

TX_IN4N

TX_IN4P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

IN0N

IN0P

TX_OUT7N

GND

I2C Address

010-0010 (0x22)

GND

VDD1V8

FG1_T2

FG2_T2

SCL1

SDA1

FG1_T2

FG2_T2

SCL1

SDA1

SCL

SDA

TX_OUT7P

TX_OUT6N

TX_IN4P

TX_IN4N

TX_IN5P

TX_IN5N

TX_IN6P

TX_IN6N

TX_IN7P

TX_IN7N

TX_OUT4P

TX_OUT4N

TX_OUT5P

TX_OUT5N

TX_OUT6P

TX_OUT6N

TX_OUT7P

TX_OUT7N

TX_OUT6P

TX_OUT5N

TX_OUT5P

TX_OUT4N

TX_OUT4P

OUT3N

OUT3P

ADDR3

ADDR4

ADDR2

ADDR1

FG2

FG1

OUT2N

OUT2P

OUT1N

OUT1P

OUT0N

OUT0P

CTL1_T2

CTL2_T2

CTL3_T2

T2_TEST1

PTNVCC1

CTL1_T2

CTL2_T2

CTL3_T2

TEST1

LCTL1

LCTL2

LCTL3

GND6

GND5

GND4

GND3

GND2

GND1

TEST2

GND

PESD3V3R1BSFD17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

39 38 37 31404142

PTN3944

PESD3V3R1BSF

Figure 5. Front side U2 redrivers schematic

User manual Rev. 1 — 14 July 2021

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

aaa-042297

C43

0.22 µF

C44

0.22 µF

C51

0.22 µF C52

0.22 µF

C53

0.22 µF C54

0.22 µF

C55

0.22 µF C56

0.22 µF

C57

0.22 µF

200 kΩ

C58

0.22 µF

C45

0.22 µF

C46

0.22 µF

C47

0.22 µF

C48

0.22 µF

C49

0.22 µF

C50

0.22 µF 34

NC1

NC2

VDD

VCCA

VCCB

VCCC

VCCD

T3_TEST1

TX_IN11N

TX_IN11P

TX_IN10N

TX_IN10P

TX_IN9N

TX_IN9P

TX_IN8N

TX_IN8P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

IN0N

IN0P

TX_OUT11N

GND

I2C Address

010-0001 (0x21)

GND

VDD1V8

FG1_T3

FG2_T3

SCL1

SDA1

FG1_T3

FG2_T3

SCL1

SDA1

SCL

SDA

TX_OUT11P

TX_OUT10N

TX_IN8P

TX_IN8N

TX_IN9P

TX_IN9N

TX_IN10P

TX_IN10N

TX_IN11P

TX_IN11N

TX_OUT8P

TX_OUT8N

TX_OUT9P

TX_OUT9N

TX_OUT10P

TX_OUT10N

TX_OUT11P

TX_OUT11N

TX_OUT10P

TX_OUT9N

TX_OUT9P

TX_OUT8N

TX_OUT8P

OUT3N

OUT3P

ADDR3

ADDR4

ADDR2

ADDR1

FG2

FG1

OUT2N

OUT2P

OUT1N

OUT1P

OUT0N

OUT0P

CTL1_T3

CTL2_T3

CTL3_T3

T3_TEST1

PTNVCC1

CTL1_T3

CTL2_T3

CTL3_T3

TEST1

LCTL1

LCTL2

LCTL3

GND6

GND5

GND4

GND3

GND2

GND1

TEST2

GND

PESD3V3R1BSFD33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

39 38 37 31404142

PTN3944

PESD3V3R1BSF

Figure 6. Front side U3 redrivers schematic

User manual Rev. 1 — 14 July 2021

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NXP Semiconductors UM11596

PTN3944 linear equalizer application board user manual

aaa-042298

C64

0.22 µF

C65

0.22 µF

C72

0.22 µF C73

0.22 µF

C74

0.22 µF C75

0.22 µF

C76

0.22 µF C77

0.22 µF

C78

0.22 µF C79

0.22 µF

C66

0.22 µF

C67

0.22 µF

C68

0.22 µF

C69

0.22 µF

C70

0.22 µF

C71

0.22 µF 34

NC1

NC2

VDD

VCCA

VCCB

VCCC

VCCD

T4_TEST1

TX_IN15N

TX_IN15P

TX_IN14N

TX_IN14P

TX_IN13N

TX_IN13P

TX_IN12N

TX_IN12P

IN3N

IN3P

IN2N

IN2P

IN1N

IN1P

IN0N

IN0P

TX_OUT15N

GND

I2C Address

010-0000 (0x20)

GND

FG1_T4

FG2_T4

SCL1

SDA1

FG1_T4

FG2_T4

SCL1

SDA1

SCL

SDA

TX_OUT15P

TX_OUT14N

TX_IN12P

TX_IN12N

TX_IN13P

TX_IN13N

TX_IN14P

TX_IN14N

TX_IN15P

TX_IN15N

TX_OUT12P

TX_OUT12N

TX_OUT13P

TX_OUT13N

TX_OUT14P

TX_OUT14N

TX_OUT15P

TX_OUT15N

TX_OUT14P

TX_OUT13N

TX_OUT13P

TX_OUT12N

TX_OUT12P

OUT3N

OUT3P

ADDR3

ADDR4

ADDR2

ADDR1

FG2

FG1

OUT2N

OUT2P

OUT1N

OUT1P

OUT0N

OUT0P

CTL1_T4

CTL2_T4

CTL3_T4

T4_TEST1

PTNVCC1

CTL1_T4

CTL2_T4

CTL3_T4

TEST1

LCTL1

LCTL2

LCTL3

GND6

GND5

GND4

GND3

GND2

GND1

TEST2

GND

PESD3V3R1BSFD49

D50

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

D64

39 38 37 31404142

GND

PTN3944

PESD3V3R1BSF

Figure 7. Front side U4 redrivers schematic

User manual Rev. 1 — 14 July 2021

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