NXP Semiconductors MC9S08LG32 Manuale utente

HCS08

Microcontrollers

freescale.com

MC9S08LG32RM

Rev. 5

8/2009

MC9S08LG32

MC9S08LG16

Reference Manual

THIS DOCUMENT CONTAINS INFORMATION ON ANEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR

DISCONTINUE THIS PRODUCT WITHOUT NOTICE.

MC9S08LG32 Series Features

8-Bit HCS08 Central Processor Unit (CPU)

• Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature

range of –40 °C to 85 °C and –40 °C to 105 °C

• HCS08 instruction set with added BGND instruction

• Support for up to 32 interrupt/reset sources

On-Chip Memory

• 32 KB or 18 KB dual array flash; read/program/erase

over full operating voltage and temperature

• 1984 byte random access memory (RAM)

• Security circuitry to prevent unauthorized access to

RAM and flash contents

Power-Saving Modes

• Two low-power stop modes (stop2 and stop3)

• Reduced-power wait mode

• Peripheral clock gating register can disable clocks to

unused modules, thereby reducing currents

• Low power on-chip crystal oscillator (XOSC) that can be

used in low-power modes to provide accurate clock

source to real time counter and LCD controller

• 100 μs typical wakeup time from stop3 mode

Clock Source Options

• Oscillator (XOSC) — Loop-control Pierce oscillator;

crystal or ceramic resonator range of 31.25 kHz to

38.4 kHz or 1 MHz to 16 MHz

• Internal Clock Source (ICS) — Internal clock source

module containing a frequency-locked-loop (FLL)

controlled by internal or external reference; precision

trimming of internal reference allows 0.2% resolution

and 2% deviation over temperature and voltage; supports

bus frequencies from 1 MHz to 20 MHz

System Protection

• COP reset with option to run from dedicated 1 kHz

internal clock or bus clock

• Low-voltage warning with interrupt

• Low-voltage detection with reset

• Illegal opcode detection with reset

• Illegal address detection with reset

• Flash and RAM protection

Development Support

• Single-wire background debug interface

• Breakpoint capability to allow single breakpoint setting

during in-circuit debugging (plus two more breakpoints

in on-chip debug module)

• On-chip in-circuit emulator (ICE) debug module

containing three comparators and nine trigger modes;

eight deep FIFO for storing change-of-flow addresses

and event-only data; debug module supports both tag and

force breakpoints

Peripherals

•LCD — Up to 4 x 41 or 8 x 37 LCD driver with internal

charge pump

•ADC — Up to 16-channel, 12-bit resolution; 2.5 μs

conversion time; automatic compare function;

temperature sensor; internal bandgap reference channel;

runs in stop3 and can wake up the system; fully

functional from 5.5 V to 2.7 V

•SCI — Full duplex non-return to zero (NRZ); LIN

master extended break generation; LIN slave extended

break detection; wakeup on active edge

•SPI— Full-duplex or single-wire bidirectional;

double-buffered transmit and receive; master or slave

mode; MSB-first or LSB-first shifting

•IIC — With up to 100 kbps with maximum bus loading;

multi-master operation; programmable slave address;

interrupt driven byte-by-byte data transfer; supports

broadcast mode and 10-bit addressing

•TPMx — One 6 channel and one 2 channel; selectable

input capture, output compare, or buffered edge or

center-aligned PWM on each channel

•MTIM — 8-bit counter with match register; four clock

sources with prescaler dividers; can be used for periodic

wakeup

•RTC — 8-bit modulus counter with binary or decimal

based prescaler; three clock sources including one

external source; can be used for time base, calendar, or

task scheduling functions

•KBI — One keyboard control module capable of

supporting 8x8 keyboard matrix

•IRQ — External pin for wakeup from low-power modes

Input/Output

• 39, 53, or 69 GPIOs

• 8 KBI and 1 IRQ interrupt with selectable polarity

• Hysteresis and configurable pullup device on all input

pins; configurable slew rate and drive strength on all

output pins

Package Options

• 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP

MC9S08LG32 Reference Manual

Covers MC9S08LG32

MC9S08LG16

Related Documentation:

•MC9S08LG32PB (Product Brief)

Contains descriptive feature set, example application

information, and developer environment details

•MC9S08LG32 Data Sheet

Contains package information, pinouts,

electricals/characterization data, and mechanical

drawings

Find the most current versions of all documents at:

http://www.freescale.com

MC9S08LG32RM

Rev. 5

8/2009

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

THIS DOCUMENT CONTAINS INFORMATION ON ANEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR

DISCONTINUE THIS PRODUCT WITHOUT NOTICE.

MC9S08LG32 MCU Series, Rev. 5

6Freescale Semiconductor

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will be

the most current. Your printed copy may be an earlier revision. To verify you have the latest information

available, refer to:

http://www.freescale.com

The following revision history table summarizes changes contained in this document.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

Revision

Number

Revision

Date Description of Changes

Rev. 1 9/2008 First Initial Release.

Rev. 2 9/2008 Second Initial Release.

Rev. 3 11/2008 Alpha Customer Release.

Rev. 4 2/2009 Launch Release.

Rev. 5 8/2009

•InChapter 3, “Modes of Operation,” added On-Chip Peripheral Modules in

Stop Modes section in Chapter 3.

•InTable 5-2, corrected addresses for vector number from 23 to 18.

•InTable 7-1, updated KBI pins order as per PINPS1 register.

• Changed TCLK, T1CH0, T1CH1, T2CH0, T2CH1, T2CH2, T2CH3, T2CH4,

T2CH5 to TPMCLK, TPM1CH0, TPM1CH1, TPM2CH0, TPM2CH1,

TPM2CH2, TPM2CH3, TPM2CH4, TPM2CH5.

• Changed ‘LCDCPEN” to “LCDPEN” and “LCDFWF” to “LCDWF.”

•InChapter 12, “Inter-Integrated Circuit (S08IICV2),” a note is added in the

introduction mentioning that MC9S08LG32 series of MCUs include only one

IIC module.

MC9S08LG32 MCU Series, Rev. 5

Freescale Semiconductor 7

List of Chapters

Chapter Title Page

Chapter 1 Device Overview ....................................................................................... 21

Chapter 2 Pins and Connections .............................................................................. 27

Chapter 3 Modes of Operation .................................................................................. 41

Chapter 4 Memory ...................................................................................................... 49

Chapter 5 Resets, Interrupts, and General System Control ................................... 73

Chapter 6 Parallel Input/Output Control................................................................... 97

Chapter 7 Keyboard Interrupt (S08KBIV2) ............................................................. 128

Chapter 8 Central Processor Unit (S08CPUV5) ..................................................... 135

Chapter 9 LCD Module (S08LCDLPV1)................................................................... 158

Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ....................................... 200

Chapter 11 Internal Clock Source (S08ICSV3)....................................................... 226

Chapter 12 Inter-Integrated Circuit (S08IICV2) ...................................................... 241

Chapter 13 Serial Communications Interface (S08SCIV4).................................... 259

Chapter 14 Serial Peripheral Interface (S08SPIV4)................................................ 278

Chapter 15 Real-Time Counter (S08RTCV1) .......................................................... 297

Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ........................................ 306

Chapter 17 Modulo Timer (S08MTIMV1) ................................................................. 327

Chapter 18 Development Support........................................................................... 337

Chapter 19 Debug Module (DBG) (64K).................................................................. 350

MC9S08LG32 MCU Series, Rev. 5

Freescale Semiconductor 9

Contents

Section Number Title Page

Chapter 1

Device Overview

1.1 Devices in the MC9S08LG32 Series ...............................................................................................21

1.2 MCU Block Diagram .......................................................................................................................22

1.3 System Clock Distribution ...............................................................................................................24

Chapter 2

Pins and Connections

2.1 Introduction ......................................................................................................................................27

2.2 Device Pin Assignment ....................................................................................................................27

2.3 Recommended System Connections ................................................................................................31

2.3.1 Power ................................................................................................................................33

2.3.2 Oscillator ...........................................................................................................................33

2.3.3 RESET ..............................................................................................................................34

2.3.4 Background / Mode Select (BKGD/MS) ..........................................................................34

2.3.5 IRQ ....................................................................................................................................35

2.3.6 LCD Pins ...........................................................................................................................35

2.3.7 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................36

Chapter 3

Modes of Operation

3.1 Introduction ......................................................................................................................................41

3.2 Features ............................................................................................................................................41

3.3 Run Mode.........................................................................................................................................41

3.4 Active Background Mode ................................................................................................................41

3.5 Wait Mode ........................................................................................................................................42

3.6 Stop Modes.......................................................................................................................................43

3.6.1 Stop2 Mode .......................................................................................................................43

3.6.2 Stop3 Mode .......................................................................................................................44

3.6.3 Active BDM Enabled in Stop Mode .................................................................................45

3.6.4 LVD Enabled in Stop Mode ..............................................................................................45

3.7 Mode Selection.................................................................................................................................45

3.7.1 On-Chip Peripheral Modules in Stop Modes ....................................................................48

Chapter 4

Memory

4.1 Introduction ......................................................................................................................................49

MC9S08LG32 MCU Series, Rev. 5

10 Freescale Semiconductor

Section Number Title Page

4.2 MC9S08LG32 Series Memory Map ................................................................................................49

4.3 Reset and Interrupt Vector Assignments ..........................................................................................50

4.4 Register Addresses and Bit Assignments.........................................................................................52

4.4.1 Reserved Flash Locations .................................................................................................59

4.5 RAM.................................................................................................................................................60

4.6 Flash .................................................................................................................................................60

4.6.1 Features .............................................................................................................................61

4.6.2 Program and Erase Times .................................................................................................61

4.6.3 Program and Erase Command Execution .........................................................................62

4.6.4 Burst Program Execution ..................................................................................................63

4.6.5 Access Errors ....................................................................................................................65

4.6.6 Flash Block Protection ......................................................................................................65

4.6.7 Vector Redirection ............................................................................................................66

4.7 Security.............................................................................................................................................66

4.8 Flash Registers and Control Bits......................................................................................................67

4.8.1 Flash Clock Divider Register (FCDIV) ............................................................................68

4.8.2 Flash Options Register (FOPT and NVOPT) ....................................................................69

4.8.3 Flash Configuration Register (FCNFG) ...........................................................................70

4.8.4 Flash Protection Register (FPROT and NVPROT) ..........................................................70

4.8.5 Flash Status Register (FSTAT) ..........................................................................................71

4.8.6 Flash Command Register (FCMD) ...................................................................................72

Chapter 5

Resets, Interrupts, and General System Control

5.1 Introduction ......................................................................................................................................73

5.2 Features ............................................................................................................................................73

5.3 MCU Reset.......................................................................................................................................73

5.4 Computer Operating Properly (COP) Watchdog..............................................................................74

5.5 Interrupts ..........................................................................................................................................75

5.5.1 Interrupt Stack Frame .......................................................................................................76

5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................76

5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................77

5.6 Low-Voltage Detect (LVD) System .................................................................................................79

5.6.1 Power-On Reset Operation ...............................................................................................79

5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................79

5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................79

5.7 Peripheral Clock Gating ...................................................................................................................79

5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................80

5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................80

5.8.2 System Reset Status Register (SRS) .................................................................................82

5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................83

5.8.4 System Options Register 1 (SOPT1) ................................................................................84

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