Quatech Asynchronous Communications Adapter for PCI bus... Manuale utente

DSCLP/SSCLP-100

Two Channel Low Profile RS-232

Asynchronous Communications Adapter

for PCI bus

User's Manual

QUATECH, INC. TEL: (330) 655-9000

5675 Hudson Industrial Parkway FAX: (330) 655-9010

Hudson, Ohio 44236 http://www.quatech.com

1 DSCLP/SSCLP-100 User's Manual

WARRANTY INFORMATION

Quatech, Inc. warrants the DSCLP-100 or SSCLP-100 to be free of defects for

five (5) years from the date of purchase. Quatech, Inc. will repair or replace any board that

fails to perform under normal operating conditions and in accordance with the procedures

outlined in this document during the warranty period. Any damage that results from improper

installation, operation, or general misuse voids all warranty rights.

Please complete the following information and retain for your records. Have this

information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: DSCLP-100 or SSCLP-100

PRODUCT DESCRIPTION: Two or One Channel Low Profile RS-232

Asynchronous PCI Bus Communications Adapter

SERIAL NUMBER:

2006, Quatech, Inc.

NOTICE

The information contained in this document cannot be reproduced in any

form without the written consent of Quatech, Inc. Likewise, any software

programs that might accompany this document can be used only in accordance

with any license agreement(s) between the purchaser andQuatech, Inc. Quatech,

Inc. reserves the right to change this documentation or the product to which it

refers at any time and without notice.

The authors have taken due care in the preparation of this document and

every attempt has been made to ensure its accuracy and completeness. In no event

will Quatech, Inc. be liable for damages of any kind, incidental or consequential,

in regard to or arising out of the performance or form of the materials presented in

this document or any software programs that might accompany this document.

Quatech, Inc. encourages feedback about this document. Please send any

written comments to the Technical Support department at the address listed on the

cover page of this document.

DOS, Windows 95/98/2000/ME, Windows NT are trademarks or registered trademarks of

Microsoft Corporation. OS/2 is a registered trademark of IBM Corporation. All other trademarks

or registered trademarks are property of their respective owners.

3 DSCLP/SSCLP-100 User's Manual

Declaration of Conformity

Manufacturer's Name: Quatech Inc.

Manufacturer's Address: 5675 Huson Industrial Parkway

Akron, Ohio 44236 (USA)

Application of Council Directive: 89/336/EEC

Standards to which

Conformity is Declared: * EN50081-1 (EN55022,

EN60555-2, EN60555-3)

* EN50082-1 (IEC 801-2,

IEC 801-3, & IEC 801-4)

Type of Equipment: Information Technology

Equipment

Equipment Class: Commercial, Residential, & Light

Industrial

Product Name: PCI Two Port or One Port Serial

Communications Card

Model Number : DSCLP-100 / SSCLP-100

4 DSCLP/SSCLP-100 User's Manual

Table of Contents

10 Troubleshooting .................................

9 Specifications ......................................

8 PCI Resource Map ...............................

7 External Connections ............................

6.3.1 QTPCI.EXE ..................................... 31

6.3 DOS and other operating systems ................... 31

6.2 OS/2 ............................................... 31

6.1 Windows NT ....................................... 31

6 Other Operating Systems .......................

5.6.1 Changing Resource Settings with Device Manager .21

5.6 Viewing Resources with Device Manager ............ 20

5.5 Using the "New Hardware Found" Wizard .......... 20

5.4 Windows 95 ........................................ 19

5.3 Windows 98 ........................................ 18

5.2 Windows 2000 ...................................... 17

5.1 Windows Millennium ............................... 17

5 Windows Configurations ........................

4.4.2 Clock Rate Multiplier ............................ 15

4.4.1 Enhanced Serial Adapter Identification ........... 15

4.4 Options Register .................................... 14

4.3 Interrupt Status Register ............................ 14

4.2 Enabling the Special Registers ...................... 13

4.1 Base Address and Interrupt Level (IRQ) ............. 13

4 Address Map and Special Registers ...........

3 Hardware Installation ...........................

2.3 Force High-Speed UART Clock (X2 or X4, J4-J5) .... 9

2.2 Enable Scratchpad Register (SPAD, J2) .............. 9

2.1 Factory Default Configuration ....................... 9

2 Hardware Configuration .........................

1 General Information ..............................

5 DSCLP/SSCLP-100 User's Manual

1 General Information

The Quatech, Inc. DSCLP-100 (two-port) and SSCLP-100 (one-port)

provide RS-232 asynchronous serial communication interfaces for Low Profile

IBM-compatible personal computer systems using the PCI expansion bus. The

DSCLP-100 uses Quatech's new Enhanced Serial Adapter design. Legacy serial

port data rates are limited to a maximum of 115,200 bits per second. This manual

usually refers to the DSCLP-100. All information pertains equally to the

SSCLP-100, with the exception that with the SSCLP there is just one port instead

of two.As a PCI device, the DSCLP-100 requires no hardware configuration. The

card is automatically configured by the computer's BIOS or operating system.

The two serial ports share a single interrupt line and are addressed in a contiguous

block of 16 bytes. A special interrupt status register is provided to help software

to manage the shared interrupt.

The DSCLP-100's serial ports are implemented using 16550 Universal

Asynchronous Receiver/Transmitters (UARTs). These UARTs contain hardware

buffers (FIFOs) which reduce processing overhead and allow higher data rates to

be achieved.

The DSCLP-100 is supported under several popular operating systems and

environments. Contact the sales department for details on current software

offerings. Most device drivers are available for download from the Quatech world

wide web site at http://www.quatech.com.

6 DSCLP/SSCLP-100 User's Manual

2 Hardware Configuration

The DSCLP-100 is automatically configured at boot time by the

computer's BIOS or operating system. There are no required switches or jumpers

to set for installation.

This chapter lists a number of optional jumper settings that control various

hardware features. Jumpers J2, J4-J5 are grouped together at the end of the board

opposite the D-type connector (D-25 for DSCLP, D-9 for SSCLP). Any changes

from the factory default should be made before installing theDSCLP-100 in the

computer.

2.1 Factory Default Configuration

Figure 2 shows the jumper configuration as shipped from the factory, with

two spare jumpers applied in neutral positions. Remove one or both and apply as

shown in following sections to set optional features.

SPAD

Figure 2 --- Factory default jumper configuration

2.2 Enable Scratchpad Register (SPAD, J2)

In the default configuration, an Interrupt Status Register(see section 4.3)

and an Options Register (see section 4.4) replace the scratchpad (base address + 7)

of each UART. If the SPAD jumper is applied as in Figure 3, the UART

scratchpad registers are enabled, and the Interrupt Status Register and the Options

SPAD

Figure 3 --- Enable scratchpad registers

7 DSCLP/SSCLP-100 User's Manual

2.3 Force High-Speed UART Clock (X2 or X4, J4-J5)

These jumpers force an increase of the UART input clock frequency by a

factor of two or four. This feature can allow legacy software to use baud rates

above 115,200 bits per second. It is also useful if the serial port device driver

does not directly support setting the higher baud rates through the Options

If one of these jumpers is applied, it overrides any value written to the

Options Register to set the clock multiplier by software. The effective baud rate

will be either two or four times the value for which the UART itself is

programmed.

The factory default is none of these jumpers applied, which allows for

software control of the clock multiplier via the Options Register. The Options

compatibility with standard serial ports.

SPAD

Force times-two clock

Baud rates u

to 230.4 kb

SPAD

Factory default

software control

SPAD

Force times-four clock

Baud rates u

to 460.8 kb

Figure 4 --- Clock multiplier jumper options

8 DSCLP/SSCLP-100 User's Manual

3 Hardware Installation

1. Turn off the power of the computer system in which the DSCLP-100 is to

be installed.

2. Remove the system cover according to the instructions provided by the

computer manufacturer.

3. Make any desired optional jumper setting changes.

4. Install the DSCLP-100 in any empty PCI expansion slot. The board

should be secured by installing the Option Retaining Bracket (ORB)

screw.

5. Replace the system cover according to the instructions provided by the

computer manufacturer.

6. Attach and secure the cable connectors to the desired equipment.

7. Turn on the power of the computer system.

The output of the DSCLP-100 is a 25-pin D-connector. A cable is

provided to convert the D-25 into two standard male D-9 connectors with all

control signals provided to each port (RTS, DTR, CTS, DSR, DCD, and RI).

The output of the SSCLP-100 is one standard male D-9 connector.

J5 X2

SPAD

Clock multiplier/

scratchpad select

Figure 5 --- Jumper/connector locations

9 DSCLP/SSCLP-100 User's Manual

4 Address Map and Special Registers

This chapter explains how the two UARTs and special registers are

addressed, as well as the layout of those registers. This material will be of interest

to programmers writing driver software for the DSCLP-100.

4.1 Base Address and Interrupt Level (IRQ)

The base address and IRQ used by the DSCLP-100 are determined by the

BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The

two ports reside in a single block of I/O space in eight byte increments, for a total

of 16 contiguous bytes, as shown in Figure 6.

Base Address + 8 to Base Address + 15Serial 2

Base Address + 0 to Base Address + 7Serial 1

I/O Address RangePort

Figure 6 --- Port Address Map

All serial ports share the same IRQ. The DSCLP-100 signals a hardware

interrupt when any port requires service. The interrupt signal is maintained until

no port requires service. Interrupts are level-sensitive on thePCI bus.

The base address and IRQ are automatically detected by the device drivers

Quatech supplies for various operating systems. For cases where no device driver

is available, such as for operation under DOS, Quatech supplies the "QTPCI"

DOS software utility for manually determining the resources used. Seesection

6.3.1 for details.

10 DSCLP/SSCLP-100 User's Manual

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