Samsung S5PV210 Guida

S5PV210_HARDWARE DESING GUIDE REV 1.0

Hardware Design

Guide

S5PV210

RISC Microprocessor

FEB 8, 2010

REV 1.0

S5PV210_HARDWARE DESING GUIDE REV 1.0

Important Notice

The information in this publication has been carefully

checked and is believed to be entirely accurate at the

time of publication. Samsung assumes no

responsibility, however, for possible errors or

omissions, or for any consequences resulting from the

use of the information contained herein.

Samsung reserves the right to make changes in its

products or product specifications with the intent to

improve function or design at any time and without

notice and is not required to update this

documentation to reflect such changes.

This publication does not convey to a purchaser of

semiconductor devices described herein any license

under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or

guarantee regarding the suitability of its products for

any particular purpose, nor does Samsung assume

any liability arising out of the application or use of any

product or circuit and specifically disclaims any and all

liability, including without limitation any consequential

or incidental damages.

"Typical" parameters can and do vary in different

applications. All operating parameters, including

"Typicals" must be validated for each customer

application by the customer's technical experts.

Samsung products are not designed, intended, or

authorized for use as components in systems

intended for surgical implant into the body, for other

applications intended to support or sustain life, or for

any other application in which the failure of the

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Should the Buyer purchase or use a Samsung product

for any such unintended or unauthorized application,

the Buyer shall indemnify and hold Samsung and its

officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs,

damages, expenses, and reasonable attorney fees

arising out of, either directly or indirectly, any claim of

personal injury or death that may be associated with

such unintended or unauthorized use, even if such

claim alleges that Samsung was negligent regarding

the design or manufacture of said product

S5PV210_HARDWARE DESING GUIDE REV 1.0

S5PV210 RISC Microprocessor

Hardware Design Guide, Revision 1.0

any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior

written consent of Samsung Electronics.

Samsung Electronics Co., Ltd.

San #24 Nongseo-Dong, Giheung-Gu

Yongin-City, Gyeonggi-Do, Korea 446-711

TEL : (82)-(031)-209-4356

FAX : (82)-(031)-209-3262

Home Page: http://www.samsungsemi.com

Printed in the Republic of Korea

S5PV210_HARDWARE DESING GUIDE REV 1.0

Revision History

Revision No Description of Change Refer to Author(s) Date

1.0 - First release version Feb 08, 2010

S5PV210_HARDWARE DESING GUIDE REV 1.0

Table of Contents

1. OVERVIEW...............................................................................................................................................8

1.1. S5PV210 Pin Information........................................................................................................................... 8

2. BALL NUMBER ASSIGNMENT .............................................................................................................63

3. POWER...................................................................................................................................................71

3.1. Pin Power Domain....................................................................................................................................71

3.2. Recommend Operating Conditions........................................................................................................73

3.3. Circuit design without level shifter........................................................................................................75

3.4. Power On/Off Sequence..........................................................................................................................76

3.5. Pin configuration guide in Sleep mode .................................................................................................78

4. SYSCON .................................................................................................................................................79

4.1. Signal Description....................................................................................................................................79

4.2. Booting Option.........................................................................................................................................81

4.3. Feature of the IROM Boot mode.............................................................................................................82

4.4. Clock..........................................................................................................................................................83

5. MEMORY SUBSYSTEM.........................................................................................................................85

5.1. Signal Description....................................................................................................................................85

5.2. TQ : Temperature Indicator.....................................................................................................................85

5.3. PCB LAYOUT GUIDELINES FOR MEMORY...........................................................................................85

6. SROM CONTROLLER............................................................................................................................88

6.1. Signal Description....................................................................................................................................88

6.2. SRAM/ROM Interface Examples .............................................................................................................89

7. ONENAND CONTROLLER.....................................................................................................................90

7.1. Signal Description....................................................................................................................................90

7.2. Circuit Diagram Example.........................................................................................................................91

8. NAND FLASH CONTROLLER ...............................................................................................................92

8.1. Signal Description....................................................................................................................................92

9. CF CONTROLLER..................................................................................................................................94

9.1. CFCON feature .........................................................................................................................................94

9.2. Signal Description....................................................................................................................................94

9.3. CF 1-slot operation guide........................................................................................................................95

9.4. CF 2-slot operation guide........................................................................................................................96

10. PWM TIMER........................................................................................................................................97

S5PV210_HARDWARE DESING GUIDE REV 1.0

10.1. Overview................................................................................................................................................97

10.2. Signal Description................................................................................................................................97

11. UART...................................................................................................................................................98

11.1. Signal descriptoin ................................................................................................................................98

12. IIC-BUS INTERFACE ..........................................................................................................................99

12.1. Pin Description .....................................................................................................................................99

12.2. Equation of the pull-up resistor value..............................................................................................100

13. SPI.....................................................................................................................................................101

13.1. Signal Description..............................................................................................................................101

13.2. EXTERNAL Loading Capacitance.....................................................................................................101

13.3. SPI Maximum Speed ..........................................................................................................................101

14. USB HOST.........................................................................................................................................102

14.1. Singnal Description............................................................................................................................102

14.2. Power Domain.....................................................................................................................................102

14.3. Circuit Diagram Example...................................................................................................................102

14.4. USB SIGNAL ROUTING......................................................................................................................103

15. USB 2.0 HS OTG...............................................................................................................................105

15.1. Signal Descriptoin..............................................................................................................................105

15.2. Power Domain.....................................................................................................................................105

16. MODEM INTERFACE........................................................................................................................107

16.1. Signal Description..............................................................................................................................107

16.2. Pin Connection Example ...................................................................................................................107

17. SD/MMC HOST CONTROLLER........................................................................................................109

17.1. Signal Description..............................................................................................................................109

17.2. Muxed Signal usage...........................................................................................................................109

18. TSI .....................................................................................................................................................111

18.1. Signal Description..............................................................................................................................111

18.2. Connection Example..........................................................................................................................111

19. DISPLAY CONTROLLER..................................................................................................................112

19.1. Signal Description..............................................................................................................................112

19.2. VD signal connection.........................................................................................................................113

19.3. VD signal connection at each bpp mode.........................................................................................114

20. CAMERA INTERFACE......................................................................................................................116

20.1. Signal Description..............................................................................................................................116

20.2. Camera INPUT.....................................................................................................................................117

S5PV210_HARDWARE DESING GUIDE REV 1.0

20.3. Restriction...........................................................................................................................................117

21. MIPI DSI & CSI..................................................................................................................................118

21.1. Signal Description..............................................................................................................................118

21.2. Design Guide.......................................................................................................................................119

22. TV ENCODER....................................................................................................................................120

22.1. Signal Description..............................................................................................................................120

23. HDMI..................................................................................................................................................121

23.1. Overview..............................................................................................................................................121

23.2. Signal Description..............................................................................................................................121

23.3. Circuit Diagram Example...................................................................................................................122

23.4. PCB Artwork Guide............................................................................................................................124

24. IIS MULTI AUDIO INTERFACE (V5.1)..............................................................................................126

24.1. Signal Description..............................................................................................................................126

24.2. Audio Port ...........................................................................................................................................126

25. IIS BUS CONTROLLER ....................................................................................................................128

25.1. Signal Description..............................................................................................................................128

25.2. External Clock Source .......................................................................................................................128

25.3. Connection Example..........................................................................................................................129

26. AC97 CONTROLLER........................................................................................................................130

26.1. AC97 Signal Description....................................................................................................................130

26.2. Audio Ports .........................................................................................................................................130

26.3. Connection Example..........................................................................................................................130

27. PCM BUS CONTROLLER.................................................................................................................131

27.1. Signal Description..............................................................................................................................131

27.2. External Clock Source .......................................................................................................................132

27.3. Connection Example..........................................................................................................................132

28. SPDIF ................................................................................................................................................134

28.1. Signal Description..............................................................................................................................134

29. ADC&TOUCH SCREEN INTERFACE...............................................................................................135

30. KEYPAD INTERFACE.......................................................................................................................136

S5PV210_HARDWARE DESING GUIDE REV 1.0

1. Overview

1.1. S5PV210 Pin Information

Definitions

Available Usage(AU)

- G/E/W : GPIO & EINT & Wake up source

- G/E : GPIO & EINT

- G : GPIO

- D : Dedicated signal

- I : Internally connected to MCP and ball out

- I(x) : Internally connected to MCP and No ball out

RET @ Power down

- No_Ret: this signal doesn’t have a retention function in power down mode

- Ret_IO : this signal has a retention function in power down mode and released by setting Enable_GPIO bit

(others[31])

- Ret_IO (sleep) : this signal has a retention function in only sleep mode and released by setting Enable_GPIO bit

(others[31])

- Ret_CF : this signal has a retention function in power down mode and released by setting Enable_CF_IO bit

(others[30])

- Ret_MMC : this signal has a retention function in power down mode and released by setting Enable_ MMC_IO

bit (others[29])

- Ret_UART : this signal has a retention function in power down mode and released by setting

Enable_GPIO_UART_IO bit (others[28]) => Only Uart2, 3

- Ret_Auto : this signal has a retention in power down mode and released automatically after wakeup.

note) Need to more attention when this kinds of signals are used for GPIO,.

Because these signals move to default signal level after wakeup until S/W set to the level.

S5PV210_HARDWARE DESING GUIDE REV 1.0

GPIO

Reset

value

IO Power

Domain Ball Name Port

In/

Out Pu/

Rese

stat

Func-0 Func-1 Func-2 Func-3 AU RET @

Power

down

Not

Use

d Circuit guide

XuRXD[0] GPA0[0] GPI PD I(L) UART_0_RXD G/E Ret_IO NC

XuTXD[0] GPA0[1] GPI PD I(L) UART_0_TXD G/E Ret_IO NC

XuCTSn[0] GPA0[2] GPI PD I(L) UART_0_CTSn G/E Ret_IO NC

XuRTSn[0] GPA0[3] GPI PD I(L) UART_0_RTSn G/E Ret_IO NC

XuRXD[1] GPA0[4] GPI PD I(L) UART_1_RXD G/E Ret_IO NC

XuTXD[1] GPA0[5] GPI PD I(L) UART_1_TXD G/E Ret_IO NC

XuCTSn[1] GPA0[6] GPI PD I(L) UART_1_CTSn G/E Ret_IO NC

VDD_EXT0

XuRTSn[1] GPA0[7] GPI PD I(L) UART_1_RTSn G/E Ret_IO NC

VDD_EXT1 XuRXD[2] GPA1[0] GPI PD I(L) UART_2_RXD UART_AUDIO_

RXD G/E Ret_UA

RT NC for RP(Low Power

Audio)debugging

S5PV210_HARDWARE DESING GUIDE REV 1.0

GPIO

Reset

value

IO Power

Domain Ball Name Port

In/

Out Pu/

Rese

stat

Func-0 Func-1 Func-2 Func-3 AU RET @

Power

down

Not

Use

d Circuit guide

XuTXD[2] GPA1[1] GPI PD I(L) UART_2_TXD UART_AUDIO_

TXD G/E Ret_UA

RT NC for RP(Low Power

Audio)debugging

XuRXD[3] GPA1[2] GPI PD I(L) UART_3_RXD UART_2_CTSn G/E Ret_UA

RT NC

XuTXD[3] GPA1[3] GPI PD I(L) UART_3_TXD UART_2_RTSn G/E Ret_UA

RT NC

XspiCLK[0

] GPB[0] GPI PD I(L) SPI_0_CLK G/E Ret_IO NC

XspiCSn[0

] GPB[1] GPI PD I(L) SPI_0_nSS G/E Ret_IO NC

XspiMISO[

0] GPB[2] GPI PD I(L) SPI_0_MISO G/E Ret_IO NC

VDD_EXT0

XspiMOSI[

0] GPB[3] GPI PD I(L) SPI_0_MOSI G/E Ret_IO NC

VDD_EXT2 XspiCLK[1

] GPB[4] GPI PD I(L) SPI_1_CLK G/E Ret_IO NC

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