SiFive FE310-G000 Manuale utente

SiFive FE310-G000 Manual

v3p2

SiFive FE310-G000 Manual

Proprietary Notice

SiFive FE310-G000 Manual by SiFive, Inc. is licensed under Attribution-NonCommercial-

NoDerivatives 4.0 International. To view a copy of this license, visit http://creativecommons.org/

licenses/by-nc-nd/4.0

Information in this document is provided “as is,” with all faults.

SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether

express or implied, including, but not limited to, the implied warranties or conditions of mer-

chantability, fitness for a particular purpose and non-infringement.

SiFive does not assume any liability rising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation indirect, incidental, spe-

cial, exemplary, or consequential damages.

SiFive reserves the right to make changes without further notice to any products herein.

Release Information

Version Date Changes

v3p2 March 25, 2021 • Added Creative Commons license

v3p1 August 22, 2019 • Fixed minor error in memory map table

v3p0 January 21, 2019

• Updated formatting and chapter organization to

match newer documents

• Fixed minor error in PLIC interrupt priorities

memory map table

• Added section on performance monitoring

• Removed chapter on Config String, which is

now a deprecated standard

v2p3 October 11, 2017 Core Complex branding

v2p2 September 28, 2017

• Clarify PLIC, PMU, RTC, WDT reset values.

• Add “empty” bit to UART rxdata register map.

• General Formatting.

Version Date Changes

v2p1 September 21, 2017 Correct the location of the config string pointer

v2p0 September 15, 2017 Fold in relevant E31 Core Complex and E300 Plat-

form information

1.0.3 July 24, 2017 Correct DWAKEUP_N and AON_PMU_OUT_0 pin

assignments

1.0.2 June 12, 2017 Clarify that QFN48 is the 6x6 Standard format

1.0.1 December 20, 2016

• Add QFN48 Package Pinout

• Add Configuration String

• Rename chip to FE310-G000

1.0 November 29, 2016 HiFive1 release

Contents

1 Introduction .............................................................................................................. 8

1.1 F 310-G000 Overview ................................................................................................ 8

1.2 31 RISC‑V Core ..................................................................................................... 10

1.3 Interrupts ................................................................................................................. 10

1.4 On-Chip Memory System...........................................................................................10

1.5 Always-On (AON) Block ............................................................................................10

1.6 GPIO Complex ......................................................................................................... 11

1.7 Universal Asynchronous Receiver/Transmitter.............................................................11

1.8 Hardware Serial Peripheral Interface (SPI) ..................................................................11

1.9 Pulse Width Modulation.............................................................................................11

1.10 Debug Support ....................................................................................................... 11

2 List of Abbreviations and Terms .................................................................13

3 E31 RISC-V Core .................................................................................................. 15

3.1 Instruction Memory System........................................................................................15

3.2 Instruction Fetch Unit ................................................................................................16

3.3 xecution Pipeline .................................................................................................... 16

3.4 Data Memory System................................................................................................17

3.5 Atomic Memory Operations........................................................................................17

3.6 Hardware Performance Monitor..................................................................................17

4 emory ap ........................................................................................................... 18

5 Boot Process.......................................................................................................... 20

5.1 Non-volatile Code Options .........................................................................................20

5.1.1 Gate ROM (GROM)..........................................................................................20

5.1.2 Mask ROM (MROM)......................................................................................... 20

5.1.3 One-Time Programmable (OTP) Memory ...........................................................21

SiFive F 310-G000 Manual: v3p2 © SiFive, Inc. Page 1

5.1.4 Quad SPI Flash Controller (QSPI)......................................................................21

5.2 Reset and Trap Vectors ............................................................................................. 21

6 Clock Generation .................................................................................................22

6.1 Clock Generation Overview .......................................................................................22

6.2 PRCI Address Space Usage ......................................................................................23

6.3 Internal Trimmable Programmable 72 MHz Oscillator (HFROSC) ..................................23

6.4 xternal 16 MHz Crystal Oscillator (HFXOSC).............................................................24

6.5 Internal High-Frequency PLL (HFPLL) ........................................................................25

6.6 PLL Output Divider.................................................................................................... 28

6.7 Internal Programmable Low-Frequency Ring Oscillator (LFROSC) ................................28

6.8 Alternate Low-Frequency Clock (LFALTCLK)...............................................................29

6.9 Clock Summary ........................................................................................................ 29

7 Power odes.......................................................................................................... 31

7.1 Run Mode ................................................................................................................ 31

7.2 Wait Mode................................................................................................................ 31

7.3 Sleep Mode.............................................................................................................. 31

8 Interrupts.................................................................................................................. 33

8.1 Interrupt Concepts .................................................................................................... 33

8.2 Interrupt Operation.................................................................................................... 34

8.2.1 Interrupt ntry and xit .....................................................................................34

8.3 Interrupt Control Status Registers...............................................................................35

8.3.1 Machine Status Register (mstatus)..................................................................35

8.3.2 Machine Trap Vector (mtvec)............................................................................36

8.3.3 Machine Interrupt nable (mie).........................................................................36

8.3.4 Machine Interrupt Pending (mip).......................................................................37

8.3.5 Machine Cause (mcause).................................................................................38

8.4 Interrupt Priorities ..................................................................................................... 39

8.5 Interrupt Latency....................................................................................................... 39

9 Core-Local Interruptor (CLINT).....................................................................40

SiFive F 310-G000 Manual: v3p2 © SiFive, Inc. Page 2

9.1 CLINT Memory Map.................................................................................................. 40

9.2 MSIP Registers......................................................................................................... 41

9.3 Timer Registers ........................................................................................................ 41

10 Platform-Level Interrupt Controller (PLIC)...........................................42

10.1 Memory Map .......................................................................................................... 42

10.2 Interrupt Sources .................................................................................................... 43

10.3 Interrupt Priorities.................................................................................................... 44

10.4 Interrupt Pending Bits .............................................................................................. 44

10.5 Interrupt nables..................................................................................................... 45

10.6 Priority Thresholds .................................................................................................. 46

10.7 Interrupt Claim Process ...........................................................................................47

10.8 Interrupt Completion................................................................................................47

11 One-Time Programmable emory (OTP) Peripheral......................49

11.1 Memory Map .......................................................................................................... 49

11.2 Programmed-I/O lock register (otp_lock)................................................................50

11.3 Programmed-I/O Sequencing...................................................................................51

11.4 Read sequencer control register (otp_rsctrl)........................................................51

11.5 OTP Programming Warnings....................................................................................52

11.6 OTP Programming Procedure ..................................................................................52

12 Always-On (AON) Domain ............................................................................53

12.1 AON Power Source.................................................................................................54

12.2 AON Clocking......................................................................................................... 54

12.3 AON Reset Unit ...................................................................................................... 54

12.4 xternal Reset Circuit..............................................................................................54

12.5 Reset Cause........................................................................................................... 55

12.6 Watchdog Timer (WDT) ...........................................................................................55

12.7 Real-Time Clock (RTC)............................................................................................55

12.8 Backup Registers.................................................................................................... 55

12.9 Power-Management Unit (PMU)...............................................................................55

12.10 AON Memory Map.................................................................................................55

SiFive F 310-G000 Manual: v3p2 © SiFive, Inc. Page 3

13 Watchdog Timer (WDT) ..................................................................................58

13.1 Watchdog Count Register (wdogcount)...................................................................58

13.2 Watchdog Clock Selection ....................................................................................... 59

13.3 Watchdog Configuration Register (wdogcfg).............................................................59

13.4 Watchdog Compare Register (wdogcmp)...................................................................60

13.5 Watchdog Key Register (wdogkey)..........................................................................60

13.6 Watchdog Feed Address (wdogfeed).......................................................................61

13.7 Watchdog Configuration ..........................................................................................61

13.8 Watchdog Resets.................................................................................................... 61

13.9 Watchdog Interrupts (wdogip0)...............................................................................61

14 Power- anagement Unit (P U).................................................................62

14.1 PMU Overview........................................................................................................ 63

14.2 Memory Map .......................................................................................................... 63

14.3 PMU Key Register (pmukey)....................................................................................64

14.4 PMU Program......................................................................................................... 65

14.5 Initiate Sleep Sequence Register (pmusleep)...........................................................66

14.6 Wakeup Signal Conditioning ....................................................................................66

14.7 PMU Interrupt nables (pmuie) and Wakeup Cause (pmucause)...............................66

15 Real-Time Clock (RTC) ...................................................................................68

15.1 RTC Count Registers (rtccounthi/rtccountlo)...................................................68

15.2 RTC Configuration Register (rtccfg)......................................................................69

15.3 RTC Compare Register (rtccmp)............................................................................70

16 General Purpose Input/Output Controller (GPIO) ............................71

16.1 GPIO Instance in F 310-G000.................................................................................73

16.2 Memory Map .......................................................................................................... 73

16.3 Input / Output Values ............................................................................................... 74

16.4 Interrupts................................................................................................................ 74

16.5 Internal Pull-Ups ..................................................................................................... 74

16.6 Drive Strength......................................................................................................... 74

16.7 Output Inversion ..................................................................................................... 75

SiFive F 310-G000 Manual: v3p2 © SiFive, Inc. Page 4

16.8 HW I/O Functions (IOF) ...........................................................................................75

17 Universal Asynchronous Receiver/Transmitter (UART)...............76

17.1 UART Overview ...................................................................................................... 76

17.2 UART Instances in F 310-G000...............................................................................76

17.3 Memory Map .......................................................................................................... 77

17.4 Transmit Data Register (txdata).............................................................................77

17.5 Receive Data Register (rxdata)..............................................................................78

17.6 Transmit Control Register (txctrl).........................................................................78

17.7 Receive Control Register (rxctrl)..........................................................................79

17.8 Interrupt Registers (ip and ie)................................................................................79

17.9 Baud Rate Divisor Register (div).............................................................................80

18 Serial Peripheral Interface (SPI) ................................................................82

18.1 SPI Overview.......................................................................................................... 82

18.2 SPI Instances in F 310-G000 ..................................................................................82

18.3 Memory Map .......................................................................................................... 83

18.4 Serial Clock Divisor Register (sckdiv).....................................................................84

18.5 Serial Clock Mode Register (sckmode).....................................................................85

18.6 Chip Select ID Register (csid)................................................................................85

18.7 Chip Select Default Register (csdef).......................................................................86

18.8 Chip Select Mode Register (csmode)........................................................................86

18.9 Delay Control Registers (delay0 and delay1).........................................................87

18.10 Frame Format Register (fmt).................................................................................88

18.11 Transmit Data Register (txdata)...........................................................................89

18.12 Receive Data Register (rxdata)............................................................................90

18.13 Transmit Watermark Register (txmark)..................................................................90

18.14 Receive Watermark Register (rxmark)...................................................................90

18.15 SPI Interrupt Registers (ie and ip)........................................................................91

18.16 SPI Flash Interface Control Register (fctrl)..........................................................92

18.17 SPI Flash Instruction Format Register (ffmt)..........................................................92

19 Pulse Width odulator (PW ) ...................................................................94

SiFive F 310-G000 Manual: v3p2 © SiFive, Inc. Page 5

19.1 PWM Overview ....................................................................................................... 94

19.2 PWM Instances in F 310-G000 ...............................................................................95

19.3 PWM Memory Map .................................................................................................95

19.4 PWM Count Register (pwmcount)............................................................................96

19.5 PWM Configuration Register (pwmcfg).....................................................................97

19.6 Scaled PWM Count Register (pwms).........................................................................98

19.7 PWM Compare Registers (pwmcmp0–pwmcmp3)........................................................99

19.8 Deglitch and Sticky Circuitry...................................................................................100

19.9 Generating Left- or Right-Aligned PWM Waveforms .................................................101

19.10 Generating Center-Aligned (Phase-Correct) PWM Waveforms ................................101

19.11 Generating Arbitrary PWM Waveforms using Ganging ............................................103

19.12 Generating One-Shot Waveforms .........................................................................103

19.13 PWM Interrupts................................................................................................... 103

20 Debug .................................................................................................................... 104

20.1 Debug CSRs ........................................................................................................ 104

20.1.1 Trace and Debug Register Select (tselect)..................................................105

20.1.2 Trace and Debug Data Registers (tdata1-3)................................................105

20.1.3 Debug Control and Status Register (dcsr).....................................................106

20.1.4 Debug PC dpc .............................................................................................106

20.1.5 Debug Scratch dscratch.............................................................................106

20.2 Breakpoints .......................................................................................................... 106

20.2.1 Breakpoint Match Control Register mcontrol ................................................107

20.2.2 Breakpoint Match Address Register (maddress).............................................109

20.2.3 Breakpoint xecution ....................................................................................109

20.2.4 Sharing Breakpoints Between Debug and Machine Mode ................................109

20.3 Debug Memory Map..............................................................................................110

20.3.1 Component Signal Registers (0x100–0x1FF).................................................110

20.3.2 Debug RAM (0x400–0x43f)........................................................................111

20.3.3 Debug ROM (0x800–0xFFF)........................................................................111

21 Debug Interface................................................................................................ 112

21.1 JTAG TAPC State Machine ....................................................................................112

21.2 Resetting JTAG Logic............................................................................................113

21.3 JTAG Clocking...................................................................................................... 113

21.4 JTAG Standard Instructions ...................................................................................114

21.5 JTAG Debug Commands .......................................................................................114

22 References.......................................................................................................... 115

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