Si4430
Preliminary Rev. 0.4 5
LIST OF FIGURES
Figure 1. Si4430 RX/TX Direct-Tie Application Example ..........................................................16
Figure 2. SPI Timing..................................................................................................................18
Figure 3. SPI Timing—READ Mode ..........................................................................................19
Figure 4. SPI Timing—Burst Write Mode ..................................................................................19
Figure 5. SPI Timing—Burst Read Mode ..................................................................................19
Figure 6. State Machine Diagram..............................................................................................20
Figure 7. TX Timing...................................................................................................................24
Figure 8. RX Timing ..................................................................................................................25
Figure 9. Frequency Deviation ..................................................................................................28
Figure 10. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................29
Figure 11. FSK vs GFSK Spectrums.........................................................................................32
Figure 12. Direct Synchronous Mode Example.........................................................................34
Figure 13. Direct Asynchronous Mode Example .......................................................................34
Figure 14. FIFO Mode Example ................................................................................................35
Figure 15. PLL Synthesizer Block Diagram...............................................................................37
Figure 16. FIFO Thresholds ......................................................................................................40
Figure 17. Packet Structure.......................................................................................................41
Figure 18. Multiple Packets in TX Packet Handler ....................................................................42
Figure 19. Required RX Packet Structure with Packet Handler Disabled .................................42
Figure 20. Multiple Packets in RX Packet Handler....................................................................42
Figure 21. Multiple Packets in RX with CRC or Header Error ...................................................43
Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC ..............................45
Figure 23. POR Glitch Parameters............................................................................................53
Figure 24. General Purpose ADC Architecture .........................................................................55
Figure 25. ADC Differential Input Example—Bridge Sensor .....................................................56
Figure 26. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................57
Figure 27. Temperature Ranges using ADC8 ...........................................................................59
Figure 28. WUT Interrupt and WUT Operation..........................................................................62
Figure 29. Low Duty Cycle Mode ..............................................................................................63
Figure 30. RSSI Value vs. Input Power.....................................................................................66
Figure 31. Split RF I/Os with Separated TX and RX Connectors—Schematic .........................67
Figure 32. Split RF I/Os with Separated TX and RX Connectors—Top ....................................69
Figure 33. Split RF I/Os with Separated TX and RX Connectors—Top Silkscreen ..................69
Figure 34. Split RF I/Os with Separated TX and RX Connectors—Bottom...............................70
Figure 35. Sensitivity vs. Data Rate ..........................................................................................71
Figure 36. Receiver Selectivity..................................................................................................72
Figure 37. TX Modulation (40 kbps, 20 kHz Deviation).............................................................73
Figure 38. TX Unmodulated Spectrum (917 MHz) ....................................................................73
Figure 39. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) .................74
Figure 40. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ...........................74
Figure 41. Synthesizer Phase Noise (VCOCURR = 11) ...........................................................75
Figure 42. QFN-20 Package Dimensions................................................................................153
Figure 43. QFN-20 Landing Pattern Dimensions ....................................................................153
