Si4432
Preliminary Rev. 0.2 5
LIST OF FIGURES
Figure 1. +20 dBm Application with Antenna Diversity and FHSS ...........................................17
Figure 2. TX Timing...................................................................................................................19
Figure 3. RX Timing ..................................................................................................................19
Figure 4. SPI Timing..................................................................................................................20
Figure 5. SPI Timing—READ Mode ..........................................................................................21
Figure 6. SPI Timing—Burst Write Mode ..................................................................................21
Figure 7. SPI Timing—Burst Read Mode ..................................................................................21
Figure 8. State Machine Diagram..............................................................................................22
Figure 9. Sensitivity vs. Carrier Frequency Offset.....................................................................30
Figure 10. FSK vs GFSK Spectrums.........................................................................................32
Figure 11. Direct Synchronous Mode Example.........................................................................34
Figure 12. Direct Asynchronous Mode Example .......................................................................34
Figure 13. FIFO Mode Example ................................................................................................34
Figure 14. PLL Synthesizer Block Diagram...............................................................................37
Figure 15. FIFO Thresholds ......................................................................................................39
Figure 16. Packet Structure.......................................................................................................40
Figure 17. Multiple Packets in TX Packet Handler ....................................................................40
Figure 18. Required RX Packet Structure with Packet Handler Disabled .................................41
Figure 19. Multiple Packets in RX Packet Handler....................................................................41
Figure 20. Multiple Packets in RX with CRC or Header Error ...................................................41
Figure 21. Operation of Data Whitening, Manchester Encoding, and CRC ..............................44
Figure 22. POR Glitch Parameters............................................................................................53
Figure 23. General Purpose ADC Architecture .........................................................................55
Figure 24. ADC Differential Input Example—Bridge Sensor .....................................................57
Figure 25. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................58
Figure 26. Temperature Ranges using ADC8 ...........................................................................60
Figure 27. WUT Interrupt and WUT Operation..........................................................................63
Figure 28. Low Duty Cycle Mode ..............................................................................................63
Figure 29. GPIO Usage Examples............................................................................................65
Figure 30. RSSI Value vs. Input Power.....................................................................................67
Figure 31. Split RF I/Os with Separated TX and RX Connectors - Schematic..........................70
Figure 32. Split RF I/Os with Separated TX and RX Connectors - Top ....................................72
Figure 33. Split RF I/Os with Separated TX and RX Connectors - Top Silkscreen................... 72
Figure 34. Split RF I/Os with Separated TX and RX Connectors - Bottom ...............................73
Figure 35. Common TX/RX Connector with RF Switch - Schematic.........................................74
Figure 36. Common TX/RX Connector with RF Switch - Top ...................................................76
Figure 37. Common TX/RX Connector with RF Switch - Top Silkscreen..................................76
Figure 38. Common TX/RX Connector with RF Switch - Bottom ..............................................77
Figure 39. Antenna Diversity Reference Design - Schematic ...................................................78
Figure 40. Antenna Diversity Reference Design - Top..............................................................80
Figure 41. Antenna Diversity Reference Design - Top Silkscreen ............................................80
Figure 42. Antenna Diversity Reference Design - Bottom.........................................................81
Figure 43. Sensitivity vs. Data Rate ..........................................................................................82
Figure 44. Receiver Selectivity..................................................................................................83
Figure 45. TX Output Power vs. VDD voltage...........................................................................84
