SpinCore Technologies PulseBlaster DDS-III Manuale utente
PulseBlasterDDS™
Model DDS-III
(PCI Board SP3)
Owner’s Manual
SpinCore Technolo ies, Inc.
http://www.spincore.com
PulseBlasterDDS
Con ratulations and thank you for choosin a desi n from
SpinCore Technolo ies, Inc.
We appreciate your business!
At SpinCore we try to fully support the needs of our customers. If you
are in need of assistance, please contact us and we will strive to
provide the necessary support.
© 2000-2004 SpinCore Technologies, Inc. All rights reserved.
SpinCore Technologies, Inc. reserves the right to make changes to the product s) or information herein without notice.
PulseBlasterDDS™, PulseBlaster™, SpinCore, and the SpinCore Technologies, Inc. logos are trademarks of SpinCore
Technologies, Inc. All other trademarks are the property of their respective owners.
SpinCore Technologies, Inc. makes every effort to verify the correct operation of the equipment. This equipment version is not
intended for use in a system in which the failure of a SpinCore device will threaten the safety of equipment or person s).
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PulseBlasterDDS
Table of Contents
I. Introduction
...................................................................................................................... 5
Product Overview ................................................................................................... 5
Board Architecture ................................................................................................. 6
Block Diagram .................................................................................................... 6
Output signals..................................................................................................... 6
Timing characteristics......................................................................................... 7
Phase Coherent Switching.................................................................................. 7
Instruction set...................................................................................................... 7
External triggering .............................................................................................. 7
Status eadback................................................................................................. 7
Summary............................................................................................................. 7
Specifications.......................................................................................................... 8
DDS Specifications ............................................................................................ 8
TTL Specifications.............................................................................................. 8
Common Parameters (DDS and TTL Specifications)......................................... 8
Pulse Program Control Flow (Common)............................................................. 8
II. Installation
...................................................................................................................... 9
Installin the PulseBlasterDDS Driver................................................................... 9
For Windows XP...................................................................................................... 9
Initializin Control of the PulseBlasterDDS........................................................ 10
III. Pro rammin the PulseBlasterDDS
.................................................................................................................... 11
Instruction Set Architecture.................................................................................. 11
Machine-Word Definition................................................................................... 11
Breakdown of 80-bit Instruction Word............................................................... 11
Usin C Functions to Pro ram the PulseBlasterDDS........................................ 13
Example Use of C Functions............................................................................ 15
IV. Connectin to the PulseBlasterDDS Board
.................................................................................................................... 17
Connector Information.......................................................................................... 17
SMA Connectors labeled DAC_OUT_0, DAC_OUT_1, and DAC_OUT_2.......17
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PulseBlasterDDS
DB-25 - TTL Output Signal Bits........................................................................ 17
IDC Connector Status - Pin Assignments......................................................... 18
Header JP100................................................................................................... 18
SMA Connector labeled “SMA0”....................................................................... 18
SMA Connector labeled “SMA400”................................................................... 18
Appendix I: Sample C pro ram
.................................................................................................................... 19
Example Pro ram.................................................................................................. 19
Appendix II: Pro rammin the PulseBlasterDDS Usin Direct Outputs.
22
Usin DLL Functions to Send Instructions......................................................... 22
Building Instructions Using the DLL Functions................................................. 22
Pro rammin Information..................................................................................... 22
Example Pro ram.................................................................................................. 24
Contact Information
.................................................................................................................... 27
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PulseBlasterDDS
I. Introduction
Product Overview
The PulseBlasterDDS series of Intelligent Pattern and Waveform Generation boards from SpinCore
Technologies, Inc., couples SpinCore’s unique Intelligent Pattern Generation processor core, dubbed
PulseBlaster, with Direct Digital Synthesis DDS) for use in system control and pulse generation.
The PulseBlaster’s state-of-the-art timing processor core provides all the necessary timing control
signals required for overall system control and pulse synchronization. By adding DDS features,
PulseBlasterDDS can now provide not only digital TTL) but also analog output signals, meeting high-
performance and high-precision complex excitation/stimuli needs of demanding users.
PulseBlasterDDS provides users the ability to control their systems through the generation of fully
synchronized digital and analog) excitation pulses from a small form factor PC board, providing users a
compelling price/performance proposition unmatched by any other device on the market today. Figure 1
presents sample capabilities of the board.
Fi ure 1: Sample PulseBlasterDDS output capabilities
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PulseBlasterDDS
Board Architecture
Block Diagram
Figure 2 presents the general architecture of the PulseBlasterDDS system. The two major building
blocks are the DDS Core and the Pulse Programming and Timing Processor Core PP Core). The
DDS Core contains a numerically controlled oscillator and has 16 programmable frequency registers
that are under the pulse program control. Prior to gating, the DDS signal can be phase offset by one of
two sets of 16 programmable phase registers. The PP Core controls the timing of the gating pulses
and provides the necessary control signals for frequency and phase registers. The DDS and PP cores
have been integrated onto a single silicon chip. High performance DAC chips and high current output
amplifiers complement the design. User control to the system is provided through the host-
programming interface over the PCI bus.
Fi ure 2: PulseBlasterDDS board architecture
Output signals
The PulseBlasterDDS comes with three analog output channels configured to output radio-frequency
RF/IF) pulses, and 10 digital output signal lines one of the output lines has a dual use and
functions as a phase reset for the DDS generator). The frequency and phase of the RF pulses generated
by the DDS are under the control of the user and are specified through software programming. The phase
of the numerically controlled oscillator can be reset on demand within the pulse program.
PulseBlasterDDS provides the ability to gate the output of the DDS channels allowing for independent
pulsed RF operation. With digital sampling rate of 100 MHz max. reference clock frequency), the
maximum theoretical output frequency is 50 MHz the Nyquist Theorem). 1 The analog output signal is
available on an on-board SMA connector. The output impedance of the analog signal is 50-ohms. There
are no interpolating filters on board.
1 Note that the usefulness of a waveform with two samples per period is limited, and, depending on applications,
practical considerations would often call for more than two samples per period.
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DAC
RF
Outputs
(SMA)
Phase0-15 Gate
Numerically
Conrolled
Oscillator
DAC
Gate
Phase0-15
Freq0-15
Reference Clock
Oscillator
Precision Timing Processor Output and Control Register
TTL
Outputs
(DB-25)
SRAM
Host Programming Interface
User Control PulseBlasterDDS-III
© 2004 SpinCore Technologies, Inc.
http://www.spincore.com
Gate DAC
DDS Core
Pulse Timing
Core
Tx
Rx
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PulseBlasterDDS
The 10 individually controlled digital TTL/CMOS) output bits are capable of delivering ±25 mA per
bit and have an output voltage of 3.3V. These signals are available on the PC bracket-mounted DB-25
connector. Setting output bit 10 high via the output control word also resets the phase of the RF
waveforms for phase coherent switching, and can be used to generate a constant voltage on the
DACs.
Timing characteristics
PulseBlasterDDS’s timing controller can accept either an internal on-board) crystal oscillator or
an external frequency source of up to 100 MHz. The innovative architecture of the timing controller
allows the processing of either simple timing instructions delays of up to 232 = 4,294,967,296 clock
cycles), or double-length timing instructions up to 252 clock cycles long – nearly 2 years with a 100
MHz clock!). Regardless of the type of timing instruction, the timing resolution remains constant for
any delay – just one clock period e.g., 10 ns for a 100 MHz clock).
The timing controller has a very short minimum delay cycle – only nine clock periods. This
translates to a 90 ns minimum pulse/delay/update with a 100 MHz clock.
Phase Coherent Switching
The board allows for phase continuous and/or phase coherent switching. In addition, the DDS
can be reset to zero whenever a new RF pulse is started. Consult the explanation of the flags
parameter to the pb_inst instruction on page 12 for implementing the phase reset.
Instruction set
PulseBlasterDDS’ design features a set of commands for highly flexible program flow control. The
micro-programmed controller allows for programs to include branches, subroutines, and loops at up to
8 nested levels – all this to assist the user in creating dense pulse programs that cycle through
repetitious events, especially useful in numerous multidimensional spectroscopy and imaging
applications.
External triggering
PulseBlasterDDS can be triggered and/or reset externally via dedicated hardware lines. The two
separate lines combine the convenience of triggering e.g., in cardiac gating) with the safety of the
"stop/reset" line. The required control signals are “active low” or short to ground).
Status Read ack
The status of the program can be read in hardware or software. The hardware status output
signals consist of five IDC connector pins labeled “Status”. The same output can be read through
software using C. See section IV Connecting to the PulseBlaster Board, page 16) for more detail
about the hardware lines and section III Programming the PulseBlaster, page 11) for more detail
about the C function status_readback ).
Summary
PulseBlasterDDS is a versatile, high-performance pulse/pattern TTL and RF/IF generator
operating at speeds of up to 100 MHz and capable of generating pulses/delays/intervals ranging from
90 ns to over 2 years per instruction. It can accommodate pulse programs with highly flexible control
commands of up to 32k program words. Its high-current output logic bits are independently controlled
with a voltage of 3.3 V. The output impedance of the analog channel is 50-ohms.
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PulseBlasterDDS
Specifications
DDS Specifications
•100 MHz reference clock oscillator other frequencies available upon request)
•0.047 Hz frequency resolution 32 bits)
•16 loadable frequency registers for agile frequency modulation/switching/selection 32 bits
each)
•Two sets of 16 loadable phase-offset registers for agile phase modulation/switching/selection
12 bits each)
•0.09° phase resolution 12 bits)
•40 ns phase switching latency
•40 ns frequency switching latency phase continuous)
•phase coherent switching
•10 dBm RF output power
•50 ohm output impedance
•SMA connectors
•30 MHz 3dB bandwidth
•RF Output capable of outputting DC at programmed output level using phase offset)
TTL Specifications
•10 individually controlled digital output lines TTL levels; one of the output lines has a dual use
and functions as a phase reset for the DDS generator)
•variable pulses/delays for every TTL line
•25 mA output current per TTL line
•output lines can be combined to increase the max. output current
Common Parameters (DDS and TTL Specifications)
•90 ns shortest pulse/interval per instruction
•2 years longest pulse/interval per instruction
•10 ns pulse/interval resolution
•RF and TTL pulses are synchronized
•32k max. memory space
•external triggering and reset – TTL levels
Pulse Program Control Flow (Common)
•loops, nested 8 levels deep
•20 bit loop counters max. 1,048,576 repetitions)
•subroutines, nested 8 levels deep
•wait for trigger - 80 ns latency, adjustable to 2 years in duration
•Approximately 2 MHz max. re-triggering frequency based on the latency of the WAIT opcode)
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PulseBlasterDDS
II. Installation
Installin the PulseBlasterDDS Driver
1. Go to http://www.pulseblaster.com/CD/PulseBlasterDDS/PCI/SP3 and download sp3.zip.
2. Unzip the files to their own directory.
3. Turn off your computer.
4. Insert the PulseBlasterDDS board into an empty PCI slot. Secure the bracket firmly with a screw.
5. Turn on your computer.
For Windows XP
6. After booting, the “Found New Hardware Wizard” should appear. Choose “Install from a list or specific
location” and click Next
7. Choose “Include this location in the search” and browse to the directory you unzipped the drivers to.
Click next.
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PulseBlasterDDS
8. While windows installs the driver, a “Files Needed” dialog may pop up. Choose the directory you
unzipped the drivers to, and click ok.
9. When finished, you should see this window.
NOTE: On some systems after you install your PulseBlasterDDS board you may need to run “Install.bat”
located in the “post_installation_files.zip” file located at
http://www.pulseblaster.com/CD/PulseBlasterDDS/PCI/SP3/old_version/post_installation_files.zip
in order for your board to work.
You are now ready to control the PulseBlasterDDS board
Initializin Control of the PulseBlasterDDS
3. Run the included “SP3_Test.exe”.
If equipped with a 100 MHz reference clock oscillator, the board should now output a 6.250MHz sine
wave on the SMA connectors labeled “DAC_OUT_0”, “DAC_OUT_1”, and “DAC_OUT_2”. The 10
TTL output lines should toggle every second.
The PulseBlasterDDS oard is now ready for use!
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