ST AN1235 Istruzioni per l'installazione e il funzionamento

October 2012 Doc ID 7272 Rev 8 1/14

AN1235

Application note

IPAD™, 500 µm Flip Chip:

package description and recommendations for use

Introduction

This document provides package and usage recommendation information for 500 µm pitch

Flip Chips. For information on 400 µm Flip Chips, see Application note AN2348.

The competitive market of portable equipment, notably the mobile phone market, is driven

by a challenging development of highly integrated products. To allow manufacturers of

portable equipment to reduce the dimension of their products, STMicroelectronics has

developed packages with reduced size, thickness and weight in the form of the Flip Chip.

The electrical performance of such components in Flip Chips is improved thanks to shorter

connections than the ones in standard plastic packages (such as TSSOP, SSOP or BGA).

Figure 1. Typical Flip-Chip package

The Flip-Chip package family has been designed to fulfill the same quality levels and the

same reliability performance as standard semiconductor plastic packages. This means

these new Flip-Chip packages should be considered as new surface mount devices which

will be assembled on a printed circuit board (PCB) without any special or additional process

steps required. In particular this package does not require any extra under fill to increase

reliability performances or to protect the device. This package is compatible with existing

pick and place equipment for board mounting. Only lead-free, RoHS compliant Flip Chips

are available in mass production.

This application note addresses the following topics:

■Product description

■Mechanical description

■Packing specifications and labeling description

■Recommended storage and shipping instructions

■Soldering assembly recommendations

■User responsibility and returns

■Changes

■Delivery quantity

■Quality

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Product description AN1235

2/14 Doc ID 7272 Rev 8

1 Product description

The Flip Chips are manufactured with a wafer level process, which STMicroelectronics has

developed, by attaching solder bumps on I/O pads of the active wafer side, thus allowing

bumped dice to be produced. The I/O contact layout can be either matrix shape or set on the

periphery. No redistribution layer is used. This allows parasitic inductances coming from the

redistribution metal tracks to be minimized.

Lead-free bump composition is 98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni. This is fully

compatible with standard lead-free reflow processes. The bump dimension (310 µm bump

diameter) allows the pick and place process to be compatible with existing equipment (in

particular with equipment used for ball grid array - BGA packages) and makes it also

compatible with the PCB design rules used for standard ICs.

Optional coating on the flat side of the package is available.

These components are delivered in tape and reel packing with the bumps on the bottom

side (placed on the bottom of the carrier tape cavity). The other face of the component is flat

and allows picking as in the standard SMD packages.

Devices are 100% electrically tested before packing. The product references are marked

on the flat side of the device.

2 Mechanical description

Mechanical dimensions of Flip Chips are provided through a product example in Figure 2.

Bumps are lead-free. Bump composition is 98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni alloy

with a near eutectic melting point of 218 to 227 °C. Die size and bump count are adapted to

the connection requirements.

Figure 2. Mechanical dimensions of a 5 x 5 bump matrix array (sample).

Note: The package height of 0.65 mm (0.695 mm for optionally coated packages) is valid for a die

thickness of 0.40 mm. With a die thickness of 0.64 mm the total height is 0.89 mm.

2.42 mm ± 50 µm

310 µm ± 50

250 µm ± 40 250 µm ± 40

500 µm ± 50

500 µm ± 50 650 µm ± 65 695 µm ± 70

Optional

coating

AN1235 Packing specifications and labeling description

Doc ID 7272 Rev 8 3/14

The Flip Chip tolerance on bump diameter and bump height are very tight. This constant

bump shape ensures a good coplanarity between bumps. Optical measurements performed

through vertical focuses show a bump plus die coplanarity below 80 µm.

Typical product marking for the flat side is shown on Figure 3. (product example). The

Flip Chip has a pin marker - A1 (see Figure 1) on both the flat side and the bump side so

that the orientation of the component can be easily determined before and after assembly.

The dots marked on the flat side and on the bump side have been designed so that they can

be detected by standard vision systems.

Marking dimensions are linked to the die size.

Figure 3. Flip-Chip marking example for 5x5 bump matrix array.

3 Packing specifications and labeling description

Flip Chips are delivered in tape and reel to be fully compatible with standard high volume

SMD components. The features of tape and reel materials are in accordance with

EIA-481-D, IEC 60286-3 and EIA 763 (783) standards. All features not specified in this

section are in accordance with EIA-481-D, IEC 60286-3 and EIA 763 (783) standards.

3.1 Carrier tape

Flip Chips are placed in the carrier tape with their bump side facing the bottom of the cavity

so that the components can be picked-up by their flat side. No flipping of the package is

necessary for mounting on PCB. The products are positioned in the carrier tape with pin A1

on the sprocket hole side. Carrier tape mechanical dimensions are shown in the example in

Figure 4. Standard tape width is 8 mm for die sizes smaller than 3 mm (dimension B0).

Note: 12 mm carrier tape width may be used for a larger die size to be in line with EIA standards.

Dot, ST logo

ECOPACK status

xx = marking

yww = datecode

(y = year

ww = week)

When very small die sizes leave

insufficient space, the ST logo and

ECOPACK symbol are omitted from

the marking.

z = manufacturing location

Packing specifications and labeling description AN1235

4/14 Doc ID 7272 Rev 8

Figure 4. Tape dimensions for Flip Chips (650 µm thickness)

The cavities in the carrier tape have been designed to avoid any damage to the

components. No hole is present in the cavity to avoid any impact or any external

contamination to the solder bumps.

The embossed carrier tape is in a black conductive material (surface resistivity within

10E4 and 10E8 ohm/sq). Use of this material protects the component against damage from

electrostatic discharge and ensures the total discharge of the component prior to placement

on the PCB. Conductivity is guaranteed to be constant and not affected by shelf life or

humidity. The material will not break when bent and does not have any residue to rub off,

powder, or flake.

3.2 Cover tape

The carrier tape is sealed with a transparent, antistatic (surface resistivity within

10E5 ohm/sq and 10E11 ohm/sq) polyester film cover tape with a heat activated adhesive.

The cover tape tensile strength is higher than 10 N.

The peeling force of the cover tape is between 0.08 N and 0.5 N in accordance with the

testing method EIA-481-D and IEC 60286-3. Cover tape is peeled back in the direction

opposite to the carrier tape travel; the angle between the cover tape and the carrier tape is

between 165 and 180 degrees and the test is done at a speed of 120 ± 10% mm/minute.

Table 1. Tape cavity sizing

Dimension Die with both sides

smaller than or equal to 1.5 mm Die with one side larger than 1.5 mm

A0 and B0 Die side size + 70 µm Cavity dimensions established to ensure that

component rotation cannot exceed 5° max.

Dot identifying bump A1 location

A1 bump location may vary with product layout

User direction of unreeling

Typical dimensions in mm

4.0

2.0

8.0

1.75

3.5

Ø 1.55

0.73

1.24

0.20

xxz

yww

xxz

yww

xxz

yww

1.24

xxz

yww

AN1235 Packing specifications and labeling description

Doc ID 7272 Rev 8 5/14

3.3 Reels

The sealed carrier tape with the Flip Chip is reeled on seven-inch reels (see Figure 5. for

reel mechanical dimensions). These reels are compliant with the EIA-481-C standard. In

particular, they are made of an antistatic polystyrene material. Color of the reel may vary

depending on supplier.

Dice quantity per reel is 5000 (with typical package thickness equal to 650 µm). In

compliance with IEC 60286-3, each reel contains a maximum of 0.1% empty cavities. Two

successive empty cavities are not allowed. Each reel may contain components coming from

2 different wafer lots.

Each reel has a minimum leader of 400 mm and a minimum trailer of 160 mm (compliant

with EIA 481-C and IEC 60286-3 standards). The leader makes up a portion of carrier tape

with empty cavities and sealed by cover tape at the beginning of the reel (external side). The

leader is affixed to the last turn of the carrier tape by using adhesive tape. The trailer is at

the end of the reel and consists of empty, sealed cavities (see Figure 6).

Figure 5. Seven-inch reel mechanical dimensions.

Figure 6. Leader and trailer

ABCDE

W1 (Hub) W2 W3

(external)

180 max

All dimensions in mm

Material: ANTISTATIC POLYSTYRENE

1.5 min 13 +0.5 8.4 +1.5 8.4 +2.5

20.2 min 60 min 14.4 max

-0.2 -0 -0.5

Leader

No components

Components

No components

Trailer

100mm min

Start

160mm min .400mm min.

Leader and trailer

End

Sealed with cover tape

User direction of feed

To p

cover

tape

Packing specifications and labeling description AN1235

6/14 Doc ID 7272 Rev 8

3.4 Final packing

Each reel is heat sealed under inert atmosphere in a transparent, recyclable and antistatic

polyethylene bag (minimum of 4 mils material thickness).

Reels are then packed in cardboard boxes.

The complete description for packing is shown on Figure 7.

Figure 7. Packing flow chart.

3.5 Labeling

To ensure component traceability, labels are stuck on the reels and the cardboard box. The

seven-inch reels and the cardboard box are identified by labels including part number,

shipped quantity and traceability references (Figure 8).

The traceability is ensured for each production lot and each shipment lot through the

labeling.

The trace code number printed on the labels ensures backward traceability from the lot

received by the customer at each step of the process - in / out dates and quantity at

diffusion, assembly, test and final store. Likewise, forward traceability is able to trace a lot

history from the wafer fab to the customer’s location.

Figure 8. Example of a reel label

dice into

the reel

Reel in a sealed

plastic bag within

inert atmosphere

The reel in its bag is packed in a

cardbox for storage & shipment

AN1235 Packing specifications and labeling description

Doc ID 7272 Rev 8 7/14

Table 2. Parameter reel label

Field Field type

Assembled in Mandatory-Country of origin

Pb-free 2nd. Level interconnect As per JEDEC Standard JESD97

MSL

Mandatory for concerned products as defined in MPI

Moisture Sensitivity Level as per JEDEC J-STD-020

Mandatory for SMD

Bag seal date For MSL 2 and above, date of vacuum sealing of dry bag

For MSL=1, “Not Moisture Sensitive” must be printed instead

PBT Peak Package Body Temperature as JEDEC J-STD-020

Mandatory for the SMD

Category Pb-free category as pr JEDEC Standard JESD97

Mandatory for concerned products as defined in MPI

Eco level Mandatory for ECOLEVEL devices only as defined in MPI

Ty p e

Mandatory

First line: Not Required

Second line: Raw line product name

Total qty Mandatory - bulk quantity

Trace code Mandatory-

Traceability code with Wafer Fab Production Area Code

Bulk ID Mandatory- Bulk ID Number, Start with A

Bar code Mandatory-Bar code area

Recommended storage, shipping instructions and descriptions AN1235

8/14 Doc ID 7272 Rev 8

4 Recommended storage, shipping instructions and

descriptions

Flip-Chip reels are packed under inert N2atmosphere in a sealed bag. For shipment and

handling, reels are packed in a cardboard box.

STMicroelectronics thus recommends the following shipping and storage conditions:

●Relative humidity between 15% and 70%

●Temperature range from -55 °C to +150 °C

Components in a non opened sealed bag can be stored 6 months after shipment.

Components in tape and reel must be protected from exposure to direct sunlight.

Moisture sensitivity level (MSL as per JEDEC J-STD-020C) is not applicable to Flip-Chip

devices since there is no plastic encapsulation and so no risk of moisture absorption and

possible related package cracks.

5 Soldering assembly recommendations

5.1 PCB design recommendations

For optimum electrical performance and highly reliable solder joints, STMicroelectronics

recommends the PCB design guidelines listed in Table 3.

To optimize the natural self centering effect of Flip Chips on PCB, PCB pad positioning and

size have to be properly designed.

Note: A too thick gold layer finishing on the PCB pad is not recommended (low joint reliability).

Micro vias

An alternative to routing on the top surface is to route out on buried layers. To achieve this,

the pads are connected to the lower layers using micro vias.

Table 3. PCB design recommendations.

PCB pad design Non solder mask defined

Micro via under bump allowed

PCB pad size Ø = 300 µm max. (circular) - 250 µm recommended

Solder mask opening Ø = 340 µm min. (for 300 µm diameter pad)

PCB pad finishing Cu - Ni (2-6 µm) - Au (0.2 µm max) oc Cu OSP (Organic Substrate

Protection)

AN1235 Soldering assembly recommendations

Doc ID 7272 Rev 8 9/14

5.2 PCB assembly guidelines

For Flip-Chip mounting on the PCB, STMicroelectronics recommends the use of a solder

stencil aperture of 330 x 330 µm maximum and a typical stencil thickness of 125 µm.

Flip Chips are fully compatible with the use of near eutectic 95.8% Sn, 3.5% Ag, 0.7% Cu

solder paste with no-clean flux. ST's recommendations for Flip-Chip board mounting are

illustrated on the soldering reflow profile shown in Figure 9.

Figure 9. ST ECOPACK®recommended soldering reflow profile for Flip-Chip

mounting on PCB (definitions)

Dwell time in the soldering zone (with temperature higher than 220 °C) has to be kept as

short as possible to prevent component and substrate damage. Peak temperature must not

exceed 260 °C. Controlled atmosphere (N2or N2H2) is recommended during the whole

reflow, especially above 150 °C.

Flip Chips are able to withstand three times the previous recommended reflow profile to be

compatible with a double reflow when SMDs are mounted on both sides of the PCB plus one

additional repair.

A maximum of three soldering reflows are allowed for these lead-free packages (with repair

step included).

The use of a no-clean paste is highly recommended to avoid any cleaning operation. To

prevent any bump cracks, ultrasonic cleaning methods are not recommended.

Table 4. ST ECOPACK®recommended soldering reflow profile for Flip-Chip

mounting on PCB (value)

Profile

Value

Typical Max.

Temp. gradient in preheat (T = 70 – 180 °C) 0.9 °C/s 3 °C/s

Temp. gradient (T = 200 – 225 °C) 2 °C/s 3 °C/s

Peak temp. in reflow 240 - 245 °C 260 °C

Time above 220 °C 60 s 90 s

Temp. gradient in cooling -2 to - 3 °C/s -6 °C/s

Time from 50 to 220 °C 160 to 220 s

250

100

150

200

240210180150120906030 300

270

-6°C/s

240-245 °C

2 - 3 °C/s

Temperature (°C) -2 °C/s

-3 °C/s

Time (s)

0.9 °C/s

60 sec

(90 max)

Soldering assembly recommendations AN1235

10/14 Doc ID 7272 Rev 8

5.3 Underfilling

Underfilling is not essential for Flip Chips. These devices can do without an underfill if the

process temperature does not exceed 175 °C and if the process time is short (typically 5

minutes).

5.4 Manual rework

Flip Chips are able to tolerate one repair in addition to the two reflows mentioned in

Section 5.2.

As for other BGA type packages the use of laser systems is the most suitable form for Flip-

Chip repair. Manual hot gas soldering is acceptable but iron soldering is not recommended.

For leaded Flip-Chip manual rework the maximum temperature allowed is 260 °C (lead-free

compatibility) and dwell time must not exceed 30 seconds.

For lead-free Flip-Chip manual rework, the maximum temperature allowed is 260 °C. The

typical soldering profile of Figure 9 can be used.

5.4.1 Rework procedure

Remove the device

Rework process starts with the removal of the device. To remove the device, heat must be

applied to melt the solder joints so that the component can be lifted from the board.

Large area bottom side preheaters may be used to raise the temperature of the board. This

may help to minimize warping of the board, and minimize the amount of heat that must be

applied on the component.

Top heating may be applied to the component by using a laser or a convective hot gas

nozzle. Nozzle size must be selected to match the component footprint appropriately. After

top heating has melted the solder, vacuum is applied through the pick-up nozzle, and the

component is lifted from the board.

The heat should be carefully directed at the component to be removed to avoid adjacent

components solder joints being reflowed. Shielding, control of gas flow from the nozzle, and

accurate temperature control are the key parameters.

Removing solder

Next step is cleaning the solder from the work site. Due to space constraints and the need

for accurate temperature control, automatic tools are recommended.

Typically, site cleaners consist of controlled non-contact gas heating and vacuuming tools.

The objective is to remove the residual solder from the site without damaging the pads,

solder masks or adjacent components, and to prepare the site for the application of a new

component.

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