Texas Instruments TAS5733L Manuale utente

8 9 10 11 12 13 14 15

Output Power (W)

PVDD (V)

RL = 4 Ω

RL = 8 Ω

Digital Audio

Processor

(DAP)

Sample Rate

Converter

(SRC)

I²C Control Port

Internal Register/State Machine Interface

Power-On Reset

(POR)

PVDDDVDD

MCLK Monitoring

and Watchdog

AVDD

PDN RST

AMP_OUT_A

AMP_OUT_C

SDIN

MCLK

SCLK

LRCK

SCL SDA

Serial Audio Port

(SAP)

Sample Rate

Auto-Detect

PLL

Digital to PWM

Converter

(DPC)

Click & Pop

Suppression

2 Ch. PWM

Modulator

Noise Shaping

Open Loop Stereo

Stereo PWM Amplifier

Sensing & Protection

Temperature

Short Circuits

PVDD Voltage

Output Current

Fault Notification

Internal Voltage Supplies

Internal Regulation and Power Distribution

AMP_OUT_B

AMP_OUT_D

DR_SD

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS5733L

SLASE77A –MARCH 2016–REVISED MARCH 2016

TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL

1 Features

1• Audio Input/Output

– One-Stereo Serial Audio Input

– Supports 44.1-kHz and 48-kHz Sample Rates

(LJ/RJ/I²S)

– Supports 3-Wire I²S Mode (no MCLK required)

– Automatic Audio Port Rate Detection

– Supports BTL and PBTL Configuration

– POUT = 10 W @ 10% THD+N

– PVDD = 12 V, 8 Ω, 1 kHz

• Audio/PWM Processing

– Independent Channel Volume Controls With

Gain of 24 dB to Mute in 0.125-dB Steps

– Programmable Three-Band Automatic Gain

Limiting (AGL)

– 20 Programmable Biquads for Speaker EQ

and Other Audio-Processing Features

• General Features

– 104-dB SNR, A-Weighted, Referenced to Full

Scale (0 dB)

– I²C Serial Control Interface w/ two Addresses

– Thermal, Short-Circuit, and Undervoltage

Protection

– Up to 90% Efficient

– AD, BD, and Ternary Modulation

– PWM Level Meter

2 Applications

• LCD TV, LED TV

• Low-Cost Audio Equipment

3 Description

The TAS5733L device is an efficient, digital-input

audio amplifier for driving stereo speakers configured

as a bridge tied load (BTL). In parallel bridge tied

load (PBTL) in can produce higher power by driving

the parallel outputs into a single lower impedance

load. One serial data input allows processing of up to

two discrete audio channels and seamless integration

to most digital audio processors and MPEG

decoders. The device accepts a wide range of input

data and data rates. A fully programmable data path

routes these channels to the internal speaker drivers.

The TAS5733L device is a slave-only device

receiving all clocks from external sources. The

TAS5733L device operates with a PWM carrier

between a 384-kHz switching rate and a 288-kHz

switching rate, depending on the input sample rate.

Oversampling combined with a fourth-order noise

shaper provides a flat noise floor and excellent

dynamic range from 20 Hz to 20 kHz.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TAS5733L HTSSOP (48) 12.50 mm × 6.10 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Power vs PVDD Simplified Block Diagram

TAS5733L

SLASE77A –MARCH 2016–REVISED MARCH 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Characteristics............................................ 6

6.5 Electrical Characteristics........................................... 6

6.6 Speaker Amplifier Characteristics............................. 7

6.7 Protection Characteristics......................................... 7

6.8 Master Clock Characteristics .................................... 7

6.9 I²C Interface Timing Requirements........................... 8

6.10 Serial Audio Port Timing Requirements.................. 8

6.11 Typical Characteristics - Stereo BTL Mode .......... 11

6.12 Typical Characteristics - Mono PBTL Mode ......... 13

7 Detailed Description............................................ 15

7.1 Overview................................................................. 15

7.2 Functional Block Diagram....................................... 15

7.3 Audio Signal Processing Overview......................... 16

7.4 Feature Description................................................. 17

7.5 Device Functional Modes........................................ 19

7.6 Programming........................................................... 20

7.7 Register Maps......................................................... 31

8 Application and Implementation ........................ 49

8.1 Application Information............................................ 49

8.2 Typical Applications ............................................... 50

9 Power Supply Recommendations...................... 55

10 Layout................................................................... 56

10.1 Layout Guidelines ................................................. 56

10.2 Layout Example .................................................... 57

11 Device and Documentation Support................. 59

11.1 Trademarks........................................................... 59

11.2 Electrostatic Discharge Caution............................ 59

11.3 Glossary................................................................ 59

12 Mechanical, Packaging, and Orderable

Information........................................................... 60

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2016) to Revision A Page

• Moved from Product Preview to Production Data release. ................................................................................................... 1

PowerPADTM

BSTRP_B

AMP_OUT_B

PGND

AMP_OUT_A

PVDD

BSTRP_A

SSTIMER

PBTL

PLL_GND

PLL_FLTM

PLL_FLTP

AVDD _REF

AVDD

ADR / FAULT

MCLK

OSC_RES

OSC _GND

DVDD_REG

PDN

BSTRP_C

AMP_OUT_C

PGND

AMP_OUT_D

PVDD

BSTRP_D

GVDD_REG

AVDD_ REG

AGND

DGND

DVDD

TEST

RST

SCL

SDA

SDIN

SCLK

LRCLK

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(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

5 Pin Configuration and Functions

DCA Package

48-Pin HTSSOP With PowerPAD™

Top View

Pin Functions

PIN TYPE(1) DESCRIPTION

NAME NO.

ADR/FAULT 19 DI/DO Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if

pulled to AVDD. Also, if configured to be a fault output by the methods described in the

Fault Indication section, this terminal will be pulled low when an internal fault occurs.

AGND 35 P Ground reference for analog circuitry (NOTE: This terminal should be connected to the

system ground)

AMP_OUT_A 6

AO Speaker amplifier outputs

AMP_OUT_B 2

AMP_OUT_C 46

AMP_OUT_D 43

AVDD 18 P Power supply for internal analog circuitry

AVDD_REF 17 P Internal power supply (NOTE: This terminal is provided as a connection point for filtering

capacitors for this supply and must not be used to power any external circuitry)

AVDD_REG 38 P Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

BSTRP_A 9

PConnection points to for the bootstrap capacitors, which are used to create a power

supply for the gate drive for the high-side device

BSTRP_B 1

BSTRP_C 48

BSTRP_D 40

DGND 34 P Ground reference for digital circuitry (NOTE: This terminal should be connected to the

system ground)

DVDD 33 P Power supply for the internal digital circuitry

DVDD_REG 23 P Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

GVDD_REG 39 P Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a

connection point for filtering capacitors for this supply and must not be used to power

any external circuitry)

LRCLK 25 DI Word select clock for the digital signal that is active on the input data line of the serial

port

TAS5733L

SLASE77A –MARCH 2016–REVISED MARCH 2016

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Product Folder Links: TAS5733L

Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NAME NO.

(2) Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground

plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the

device and into the surrounding PCB area.

MCLK 20 DI Master clock used for internal clock tree and sub-circuit/state machine clocking

NC(2)

PNot connected inside the device (all "no connect" terminals should be connected to

system ground)

OSC_GND 22 P Ground reference for oscillator circuitry (NOTE: These terminals should be connected to

the system ground)

OSC_RES 21 AO Connection point for precision resistor used by internal oscillator circuit. Details for this

resistor are shown in the Typical Applications section

PBTL 11 DI Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled

high

PDN 24 DI Places the device in power down when pulled low

PGND

—Ground reference for power device circuitry (NOTE: This terminal should be connected

to the system ground)

PLL_FLTM 15 AO Negative connection point for the PLL loop filter components

PLL_FLTP 16 AO Positive connection point for the PLL loop filter components

PLL_GND 14 P Ground reference for PLL circuitry (NOTE: This terminal should be connected to the

system ground)

PVDD

P Power supply for internal power circuitry

RST 31 DI Places the devices in reset when pulled low

SCL 29 DI I²C serial control port clock

SCLK 26 DI Bit clock for the digital signal that is active on the input data line of the serial data port

SDA 28 DI/DO I²C serial control port data

SDIN 27 DI Data line to the serial data port

SSTIMER 10 AO Connection point for the capacitor that is used by the ramp timing circuit, as described in

the SSTIMER Pin Functionality section

TEST 32 — Used by TI for testing during device production (NOTE: This terminal should be

connected to system ground)

PowerPAD — P Exposed metal pad on the underside of the device, which serves as an electrical

connection point for ground as well as a heat conduction path from the device into the

board (NOTE: This terminal should be connected to ground through a land pattern

defined in the Mechanical Data section)

TAS5733L

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SLASE77A –MARCH 2016–REVISED MARCH 2016

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.

(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.

(3) Maximum pin voltage should not exceed 6 V.

(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

VALUE UNIT

Supply voltage DVDD, AVDD –0.3 to 3.6 V

PVDD –0.3 to 20

Input voltage 3.3-V digital input –0.5 to DVDD + 0.5 V5-V tolerant(2) digital input (except MCLK) –0.5 to DVDD + 2.5(3)

5-V tolerant MCLK input –0.5 to AVDD + 2.5(3)

AMP_OUT_x to GND 22(4) V

BSTRP_x to GND 29(4) V

Operating free-air temperature 0 to 85 °C

Storage temperature range, Tstg –40 to 125 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±1500

(1) For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.

(2) 16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the

device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is

not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and

reduction in device reliability.

6.3 Recommended Operating Conditions MIN NOM MAX UNIT

DVDD, AVDD Digital, analog supply voltage 3 3.3 3.6 V

PVDD Output power devices supply voltage 8 16.5(1)

(2) V

VIH High-level input voltage 5-V tolerant 2 V

VIL Low-level input voltage 5-V tolerant 0.8 V

TAOperating ambient temperature range 0 85 °C

TJ(2) Operating junction temperature range 0 125 °C

RLLoad impedance 4 8 Ω

RLLoad impedance in PBTL 2 Ω

LOOutput-filter inductance Minimum output inductance under

short-circuit condition 10 μH

TAS5733L

SLASE77A –MARCH 2016–REVISED MARCH 2016

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Product Folder Links: TAS5733L

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

6.4 Thermal Characteristics

THERMAL METRIC(1)

DCA (48 PINS)

UNITS

Special Test

Case

JEDEC

Standard 2-

Layer PCB

JEDEC

Standard 4-

Layer PCB

TAS5733LEVM

θJA Junction-to-ambient thermal resistance(2) 50.7 27.6 25.0 °C/W

θJCtop Junction-to-case (top) thermal resistance(3) 14.9 16.7 °C/W

θJB Junction-to-board thermal resistance(4) 6.9 7.9 °C/W

ψJT Junction-to-top characterization parameter(5) 1.2 0.8 0.7 °C/W

ψJB Junction-to-board characterization parameter(6) 11.8 7.8 5.8 °C/W

θJCbot Junction-to-case (bottom) thermal resistance(7) 1.7 2.2 °C/W

6.5 Electrical Characteristics

TA= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS= 48 kHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage ADR/FAULT and SDA

IOH = –4 mA

DVDD = AVDD = 3 V 2.4 V

VOL Low-level output voltage IOL = 4 mA

DVDD = AVDD = 3 V 0.5 V

IIL Low-level input current Digital Inputs

VI< VIL

DVDD = AVDD = 3.6 V 75 μA

IIH High-level input current VI> VIH

DVDD = AVDD = 3.6 V 75 μA

IDD 3.3-V supply current 3.3-V supply voltage

(DVDD, AVDD)

Normal mode 49 68 mA

Reset (RST = low, PDN =

high) 23 38

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SLASE77A –MARCH 2016–REVISED MARCH 2016

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(1) This does not include bond-wire or pin resistance.

6.6 Speaker Amplifier Characteristics

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS= 48 KHz, RL= 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM =

384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions

and as tested on the TAS5733L EVM.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POPower output per channel

PVDD = 12 V, 10% THD, 1-kHz input signal 10

PVDD = 12 V, 7% THD, 1-kHz input signal 9

PVDD = 12 V, 1% THD, 1-kHz input signal 7.5

PVDD = 13.2 V, 10% THD, 1-kHz input signal 12

PVDD = 13.2 V, 7% THD, 1-kHz input signal 11

PVDD = 13.2 V, 1% THD, 1-kHz input signal 9

THD+N Total harmonic distortion +

noise PVDD = 12 V, PO= 1 W 0.25 %

PVDD = 13.2 V, PO= 1 W 0.3

VnOutput integrated noise (rms) A-weighted 30 μV

Crosstalk PO= 1 W, f = 1 kHz (BD Mode), PVDD = 12 V –79 dB

PO=1 W, f = 1 kHz (AD Mode), PVDD = 12 V –62 dB

Output switching frequency 11.025, 22.05, 44.1-kHz data rate ±2% 288 kHz

48, 24, 12, 8, 16, 32-kHz data rate ±2% 384

IPVDD Supply current No load (PVDD) Normal mode 16 25 mA

Reset (RST = low, PDN = high) 3 8

rDS(on)(1)

Drain-to-source resistance,

low side TJ= 25°C, includes metallization resistance 120 mΩ

Drain-to-source resistance,

high side TJ= 25°C, includes metallization resistance 120

RPD Internal pulldown resistor at

the output of each half-bridge Connected when drivers are in the high-impedance

state to provide bootstrap capacitor charge. 3 kΩ

6.7 Protection Characteristics

TA= 25°, PVDD_x = 12 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL BD mode, fS= 48 kHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Vuvp(fall) Undervoltage protection limit PVDD falling 5.4 V

Vuvp(rise) Undervoltage protection limit PVDD rising 5.8 V

OTE Overtemperature error 150 °C

IOC Overcurrent limit protection 4 A

IOCT Overcurrent response time 150 ns

(1) For clocks related to the serial audio port, please see Serial Audio Port Timing Requirements.

6.8 Master Clock Characteristics(1)

PVDD = 12 V, BTL BD mode, AVDD = DVDD = 3.3 V, fS= 48 kHz, RL= 8 Ω, audio frequency = 1 kHz, AES17 filter, fPWM =

384 kHz, TA= 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions

(unless otherwise specified).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PLL INPUT PARAMETERS

fMCLKI MCLK frequency 2.8224 24.576 MHz

MCLK duty cycle 40% 50% 60%

tr/ tf(MCLK) Rise/fall time for MCLK 5 ns

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SLASE77A –MARCH 2016–REVISED MARCH 2016

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6.9 I²C Interface Timing Requirements MIN NOM MAX UNIT

tw(RST) Pulse duration, RST active 100 μs

td(I²C_ready) Time to enable I²C after RST goes high 13.5 ms

fSCL Frequency, SCL 400 kHz

tw(H) Pulse duration, SCL high 0.6 μs

tw(L) Pulse duration, SCL low 1.3 μs

trRise time, SCL and SDA 300 ns

tfFall time, SCL and SDA 300 ns

tsu1 Setup time, SDA to SCL 100 ns

th1 Hold time, SCL to SDA 0 ns

t(buf) Bus free time between stop and start conditions 1.3 μs

tsu2 Setup time, SCL to start condition 0.6 μs

th2 Hold time, start condition to SCL 0.6 μs

tsu3 Setup time, SCL to stop condition 0.6 μs

CLLoad capacitance for each bus line 400 pF

6.10 Serial Audio Port Timing Requirements

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fSCL≤30 pF 1.024 12.28

8MHz

tsu1 Setup time, LRCK to SCLK rising edge 10 ns

th1 Hold time, LRCK from SCLK rising edge 10 ns

tsu2 Setup time, SDIN to SCLK rising edge 10 ns

th2 Hold time, SDIN from SCLK rising edge 10 ns

LRCK frequency 8 48 48 kHz

SCLK duty cycle 40% 50% 60%

LRCK duty cycle 40% 50% 60%

SCLK rising edges between LRCK rising edges 32 64 SCLK

edges

t(edge) LRCK clock edge with respect to the falling edge of SCLK –1/4 1/4 SCLK

period

tr/tfRise/fall time for SCLK/LRCK 8 ns

LRCK allowable drift before LRCK reset 4 MCLKs

SCL

SDA

th2 t(buf)

tsu2 tsu3

Start

Condition

Stop

Condition

T0028-01

SCL

SDA

tw(H) tw(L) trtf

tsu1 th1

T0027-01

tw(RST)

RST

td(I2C_ready)

System Initialization.

Enable via I C.

T0421-01

I C Active

2I C Active

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NOTE: On power up, hold the TAS5733L RST LOW for at least 100 μs after DVDD has reached 3 V.

NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is

deasserted (HIGH).

Figure 1. Reset Timing

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

th1

tsu1

t(edge)

tsu2

th2

SCLK

(Input)

LRCLK

(Input)

SDIN

T0026-04

trtf

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Figure 4. Serial Audio Port Timing

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