Texas Instruments TMS320C6201 Manuale utente

TMS320C6000 Peripherals

Reference Guide

Literature Number: SPRU190C

April 1999

Printed on Recycled Paper

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iii

Contents

Preface

Read This First

About This Manual

This reference guide describes the on-chip peripherals of the TMS320C6000

digital signal processors (DSPs). Main topics are the program memory, the data

memory,the directmemory access (DMA)controller,the enhancedDMAcontrol-

ler (EDMA), the host-port interface (HPI), the exansion bus, the external memory

interface (EMIF), the boot configuration, the multichannel buffered serial ports

(McBSPs), the timers, the interrupt selector and external interrupts, and the pow-

er-down modes.

The TMS320C62x (’C62x) and the TMS320C67x (’C67x) generations of digi-

tal signal processors make up the TMS320C6000 platform of the TMS320

family of digital signal processors. The ’C62x devices are fixed-point DSPs,

and the ’C67x devices are floating-point DSPs. The TMS320C6000 (’C6000)

is the first DSP to use the VelociTIarchitecture, a high-performance,

advancedVLIW(verylonginstructionword)architecture.TheVelocTIarchite-

churemakesthe ’C6x an excellent choice formultichannel,multifunction, and

high data rate applications.

Notational Conventions

This document uses the following conventions:

-Program listings, program examples, names are shown in a special

font. Here is a sample program listing:

LDW .D1 *A0,A1

ADD .L1 A1,A2,A3

NOP 3

MPY .M1 A1,A4,A5

-Throughout this book MSB means

most significant bit,

and LSB means

least significant bit

Registers are described throughout this book in register diagrams. Each

diagram shows a rectangle divided into fields that represent the fields of the

numbersabove, andits propertiesbelow.A legendexplains thenotation used

for the properties. For example:

31 25 24 23 22 21 20 18 17 16

FIELDA FIELDB FIELDC R, +1 RW, +0

RW, +0 RC, +x R, +0 R, +1 HRW, +0

Note: R = Readable by the CPU, W = Writeable by the CPU, +x = Value undefined after reset, +0 = Value is 0 after reset,

+1 = Value is 1 after reset, C = Clearable by the CPU, H = reads/writes performed by the host

Related Documentation From Texas Instruments

ThefollowingdocumentsdescribetheTMS320C6xfamilyandrelatedsupport

tools. To obtain a copy of any of these TI documents, call the Texas Instru-

mentsLiteratureResponseCenterat(800)477–8924.Whenordering,please

identify the book by its title and literature number.

TMS320C6000 Technical Brief

(literature number SPRU197) gives an

introductionto the ’C6000 platform ofdigital signal processors, develop-

ment tools, and third-party support.

TMS320C6000 CPU and Instruction Set Reference Guide

(literature

number SPRU189) describes the ’C6000 CPU architecture, instruction

set, pipeline, and interrupts for these digital signal processors.

TMS320C6000 Programmer’s Guide

(literature number SPRU198)

describeswaysto optimizeCandassemblycodefortheTMS320C6000

DSPs and includes application program examples.

TMS320C6000AssemblyLanguageToolsUser’sGuide

(literaturenumber

SPRU186) describes the assembly language tools (assembler, linker,

and other tools used to develop assembly language code), assembler

directives, macros, common object file format, and symbolic debugging

directives for the ’C6000 generation of devices.

TMS320C6000 Optimizing C Compiler User’s Guide

(literature number

SPRU187)describesthe’C6000Ccompilerandtheassemblyoptimizer.

ThisCcompileracceptsANSIstandardCsourcecodeandproducesas-

semblylanguagesourcecodefor the’C6000 generationof devices.The

assembly optimizer helps you optimize your assembly code.

TMS320C6x C Source Debugger User’s Guide

(literature number

SPRU188) tells you how to invoke the ’C6x simulator and emulator

versions of the C source debugger interface. This book discusses

various aspects of the debugger, including command entry, code

execution, data management, breakpoints, profiling, and analysis.

Notational Conventions / Related Documentation From Texas Instruments

TMS320C6201, TMS320C6201B Digital Signal Processors Data Sheet

(literature number SPRS051) describes the features of the

TMS320C6201 and TMS320C6201B fixed-point DSPs and provides

pinouts, electrical specifications, and timings for the devices.

TMS320C6202 Digital Signal Processor Data Sheet

(literature number

SPRS072)describesthefeaturesoftheTMS320C6202fixed-pointDSP

and provides pinouts, electrical specifications, and timings for the de-

vice.

TMS320C6701 Digital Signal Processor Data Sheet

(literature number

SPRS067) describes the features of the TMS320C6701 floating-point

DSP and provides pinouts, electrical specifications, and timings for the

device.

TMS320C6211 Digital Signal Processor Data Sheet

(literature number

SPRS073)describesthefeatures oftheTMS320C6211 fixed-pointDSP

and provides pinouts, electrical specifications, and timings for the de-

vice.

TMS320C6711 Digital Signal Processor Data Sheet

(literature number

SPRS088)describesthefeatures oftheTMS320C6711 fixed-pointDSP

and provides pinouts, electrical specifications, and timings for the de-

vice.

Trademarks

320 Hotline On-line, VelociTI, and XDS510 are trademarks of Texas

Instruments Incorporated.

PC is a trademark of International Business Machines Corporation.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SPI is a trademark of Motorola, Inc.

ST-BUS is a trademark of Mitel.

Windowsand Windows NTare registered trademarksof Microsoft Corporation.

Read This First

Related Documents / Trademarks

If You Need Assistance . . .

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If You Need Assistance

Contents

vii

Contents

1 Introduction 1Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320C6201 and TMS320C6701 DSPs and lists their key features.

1.1 TMS320 Family Overview 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 History of TMS320 DSPs 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Typical Applications for the TMS320 Family 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Overview of the TMS320C6000 Platform of DSPs 1Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Features and Options of the TMS320C6000 Devices 1Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Overview of TMS320C6000 Memory 1Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Overview of TMS320C6000 Peripherals 1Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 TMS320C6201/C6701 Program and Data Memory 2Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the program and data memory system for the TMS320C6201/C6701. This includes

program memory organization,cache modes, DMA and peripheral bus operation.

2.1 Program Memory Controller 2Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Internal Program Memory 2Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Internal Program Memory Modes 2Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Cache Architecture 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 DMA Controller Access to Program Memory 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Data Memory Controller 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Data Memory Access 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Internal Data Memory Organization 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 TMS320C6201 Revision 2 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 TMS320C6201 Revision 3 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 TMS320C6701 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.4 Data Alignment 2Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.5 Dual CPU Accesses to Internal Memory 2Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.6 DMA Accesses to Internal Memory 2Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.7 Data Endianness 2Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Peripheral Bus 2Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Byte and Halfword Access 2Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 CPU Wait States 2Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Arbitration Between the CPU and the DMA Controller 2Ć22. . . . . . . . . . . . . . . . . . .

Contents

viii

3 TMS320C6202 Program and Data Memory 3Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the 6202 program memory controller.

3.1 TMS320C6202 Program Memory Controller 3Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Memory Mapped Operation 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Cache Operation 3Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Bootload Operation 3Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 TMS320C6202 Data Memory Controller 3Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 TMS320C6211/C6711

Two-Level Internal Memory 4Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the program and data memory for the TMS320C6211/C6711.

4.1 Overview 4Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Internal Memory Control Registers 4Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 L1P Description 4Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 L1D Description 4Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 L2 Description 4Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 L2 Interfaces 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 L2 Operation 4Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 L2 EDMA Service 4Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.4 L2 Invalidation 4Ć21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Direct Memory Access (DMA) Controller 5Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the direct memory access controller operation.

5.1 Overview 5Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 DMA Registers 5Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 DMA Channel Control Registers 5Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Memory Map 5Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Initiating a Block Transfer 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 DMA Autoinitialization 5Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Transfer Counting 5Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Synchronization: Triggering DMA Transfers 5Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 Latching of DMA Channel Event Flags 5Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.2 Automated Event Clearing 5Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.3 Synchronization Control 5Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Address Generation 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Basic Address Adjustment 5Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Address Adjustment With the Global Index Registers 5Ć23. . . . . . . . . . . . . . . . . . . .

5.7.3 Element Size, Alignment, and Endianness 5Ć23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.4 Using a Frame Index to Reload Addresses 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.5 Transferring a Large Single Block 5Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.6 Sorting 5Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Split-Channel Operation 5Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.1 Split DMA Operation 5Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8.2 Split Address Generation 5Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

5.9 Resource Arbitration and Priority Configuration 5Ć30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.1 DMA Auxiliary Control Register and Priority Between Channels 5Ć30. . . . . . . . . . .

5.9.2 Switching Channels 5Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 DMA Channel Condition Determination 5Ć33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.1 Definition of Channel Conditions 5Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 DMA Controller Structure 5Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.1 Read and Write Buses 5Ć35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.2 DMA FIFO 5Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.3 Internal Holding Registers 5Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.4 DMA Performance 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 DMA Action Complete Pins 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 Emulation 5Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 EDMA Controller 6Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

This chapter describes the new enhanced DMA for the TMS320C6211/6711.

6.1 Overview 6Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 EDMA Terminology 6Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Event Processing and EDMA Control Registers 6Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Event Encoder 6Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Parameter RAM (PaRAM) 6Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.1 EDMA Transfer Parameter Entry 6Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 EDMA Transfer Parameters 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.1 Options Parameter 6Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.2 SRC/DST Address 6Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.3 Element Count 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.4 Frame/Array Count 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.5 Element/(Frame/Array) Index 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.6 Element Count Reload 6Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6.7 Link Address 6Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Initiating an EDMA Transfer 6Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7.1 Synchronization of EDMA Transfers 6Ć17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Types of EDMA Transfers 6Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.1 Non-2Dimensional Transfers 6Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8.2 2-Dimensional Transfers 6Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Linking EDMA Transfers 6Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Element Size and Alignment 6Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11 Element and Frame/Array Count Updates 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.11.1 Element Count Reload (ECRLD) 6Ć28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.12 Src/Dst Address Updates 6Ć29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13 EDMA Interrupt Generation 6Ć32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.1 EDMA Interrupt Servicing by the CPU 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.13.2 Chaining EDMA Channels by an Event 6Ć34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.14 Resource Arbitration and Priority Processing 6Ć36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.15 EDMA Performance 6Ć37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

6.16 Quick DMA (QDMA) 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.1 QDMA Registers 6Ć38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.2 QDMA Register Access 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.3 Pseudo Mappings 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.4 QDMA Performance 6Ć40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.16.5 QDMA Stalls and Priority 6Ć41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Host-Port Interface 7Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describesthehost-portinterface(HPI)usedtoaccess’C6201and’C6701memory-mapspace

by external processors.

7.1 Overview 7Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 HPI Signal Descriptions 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Data Bus: HD[15:0] 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2 Access Control Select: HCNTL[1:0] 7Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3 Halfword Identification Select: HHWIL 7Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.4 Byte Enables: HBE[1:0] 7Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.5 Read/Write Select: HR/W 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.6 Ready: HRDY 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.7 Strobes: HCS, HDS1, HDS2 7Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.8 Address Strobe Input: HAS 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.9 Interrupt to Host: HINT 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.10 HPI Bus Access 7Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 HPI Registers 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 HPI Control Register (HPIC) 7Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.2 Software Handshaking Using HRDY and FETCH 7Ć17. . . . . . . . . . . . . . . . . . . . . . .

7.3.3 Host Device Using DSPINT to Interrupt the CPU 7Ć18. . . . . . . . . . . . . . . . . . . . . . .

7.3.4 CPU Using HINT to Interrupt the Host 7Ć18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Host Access Sequences 7Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Host Initialization of HPIC and HPIA 7Ć19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 HPID Read Access Without Autoincrement 7Ć20. . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.3 HPID Read Access With Autoincrement 7Ć22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.4 Host Data Write Access Without Autoincrement 7Ć23. . . . . . . . . . . . . . . . . . . . . . . .

7.4.5 HPID Write Access With Autoincrement 7Ć25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.6 Single Halfword Cycles 7Ć26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Memory Access Through the HPI During Reset 7Ć27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Expansion Bus 8Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the expansion bus used by CPU to access off-chip peripherals, FIFOs and PCI

interface chips.

8.1 Overview 8Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Expansion Bus Signals 8Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Expansion Bus Registers 8Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.1 Expansion Bus Host Port Registers 8Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.2 Expansion Bus Global Control Register 8Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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