Texas Instruments LMK03318EVM Manuale utente

LMK03318EVM

User's Guide

Literature Number: SNAU186

November 2015

Contents

1 Overview............................................................................................................................. 6

2 Features.............................................................................................................................. 6

3 Modes of Operation.............................................................................................................. 7

4 Configuring the EVM ............................................................................................................ 7

4.1 Configuring the Power Supply.......................................................................................... 9

4.2 Configuring the Control Pins .......................................................................................... 11

4.3 Configuring the PLL Loop Filter....................................................................................... 15

4.4 Configuring the Reference Inputs .................................................................................... 16

4.5 Configuring the Clock Outputs........................................................................................ 17

4.6 Configuring the Status Outputs ....................................................................................... 17

4.7 Using the USB Interface Connection................................................................................. 17

5 EVM Quick Start Guide........................................................................................................ 18

6 EVM Layout ....................................................................................................................... 20

7 EVM Schematic.................................................................................................................. 33

8 EVM Bill of Materials........................................................................................................... 39

9 Recommended Test Instruments.......................................................................................... 42

10 Example Performance Measurements................................................................................... 43

11 Using TI’s USB2ANY Module for In-System Programming of LMK03318 ................................... 48

11.1 USB2ANY Board Connections........................................................................................ 48

11.2 Ordering a USB2ANY Module ........................................................................................ 52

2Table of Contents SNAU186–November 2015

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List of Figures

1 LMK03318EVM Photo....................................................................................................... 5

2 Power, Input, and Output Connections ................................................................................... 8

3 Power Terminals and Jumpers............................................................................................. 9

4 Control Pin Interfaces (Default Jumper Settings) ...................................................................... 11

5 Interfacing a 3.3-V LVCMOS Clock Input to SECREF_P............................................................. 16

6 Top Overlay................................................................................................................. 20

7 Top Solder Mask ........................................................................................................... 21

8 Layer 1 (Top Side) ......................................................................................................... 22

9 Layer 2....................................................................................................................... 23

10 Layer 3....................................................................................................................... 24

11 Layer 4....................................................................................................................... 25

12 Layer 5....................................................................................................................... 26

13 Layer 6....................................................................................................................... 27

14 Layer 7....................................................................................................................... 28

15 Layer 8 (Bottom Side, View from Top) .................................................................................. 29

16 Bottom Solder Mask ....................................................................................................... 30

17 Bottom Overlay ............................................................................................................. 31

18 Drill Drawing ................................................................................................................ 32

19 Soft Pin Mode, EEPROM Page 5, OUT0 – 156.25 MHz LVPECL (Spurs in dBc) ................................ 44

20 Soft Pin Mode, EEPROM Page 5, OUT2 – 125 MHz LVPECL (Spurs in dBc) .................................... 45

21 Soft Pin Mode, EEPROM Page 5, OUT4 – 100 MHz LVPECL (Spurs in dBc) .................................... 46

22 Soft Pin Mode, EEPROM Page 5, OUT6 – 25 MHz LVPECL (Spurs in dBc)...................................... 47

23 USB2ANY Module.......................................................................................................... 48

24 USB2ANY Board Connections ........................................................................................... 49

25 10-pin Cable Connection to J4 ........................................................................................... 50

26 10-pin Cable Pinout........................................................................................................ 50

27 USB2ANY Board Connector Pinout Diagram .......................................................................... 51

SNAU186–November 2015 List of Figures

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List of Tables

1 Ordering Information ........................................................................................................ 6

2 Power Configurations...................................................................................................... 10

3 Control Pin Interfaces for Soft Pin Mode or Register Default Mode (JP18 HWCTRL = LO)..................... 12

4 Control Pin Interfaces for Hard Pin Mode (JP18 HWCTRL = HI).................................................... 15

5 PLL Loop Filter C2 Selection ............................................................................................. 15

6 Soft Pin Mode - EEPROM Page Configurations (Default EVM EEPROM Image)................................. 19

7 Output RMS Jitter Summary – Soft Pin Mode, EEPROM Page 5................................................... 43

8 USB2ANY Board Connector J4 and 10-pin Cable Pinouts........................................................... 51

4List of Tables SNAU186–November 2015

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User's Guide

SNAU186–November 2015

LMK03318EVM User’s Guide

Figure 1. LMK03318EVM Photo

SNAU186–November 2015 LMK03318EVM User’s Guide

Overview

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Table 1. Ordering Information

EVM ID DEVICE ID DEVICE PACKAGE

LMK03318EVM LMK03318RHS QFN-48

1 Overview

The LMK03318EVM evaluation module provides a complete clocking platform to evaluate the clock

performance, pin-/software-configuration modes and features of the Texas Instruments LMK03318 Ultra-

Low-Jitter Clock Generator with 1 PLL, 8 outputs, 2 inputs, and integrated EEPROM.

The LMK03318EVM can be used as a flexible, multi-output clock source for compliance testing,

performance evaluation, and initial system prototyping. The onboard edge-launch SMA ports provide

access to the LMK03318 clock inputs and outputs for interfacing to test equipment and reference boards

using commercially available coaxial cables, adapters, or baluns (not included). This connectivity enables

integrated system level testing between TI’s LMK03318 and third-party FPGA/ASIC/SoC reference

boards. A software graphical user interface (GUI) platform can be installed on a Host PC to access the

LMK03318 device registers and EEPROM via the on-board USB-to-I2C interface. The GUI platform can

also be used to export / import Register and EEPROM data files to facilitate factory or in-system

programming of custom device configurations.

2 Features

• High performance, flexible clock generator with 6 independent output dividers for clocking multiple

interface standards/protocols

• Outputs up to 8 pairs of Differential or 1.8-V LVCMOS clocks, or any combination of both

– 100 Ωdifferential and 50 Ωsingle-ended output drivers

• Two selectable reference inputs

– Differential / single-ended clock or crystal input (50 MHz crystal on-board)

– Automatic or pin-controlled input selection mux to PLL

– Either reference can be directly buffered on up to 4 output pairs (bypass PLL and output dividers)

• Flexible pin modes offer multiple start-up register configuration (jumper selectable)

– Soft Pin Modes: 6 pre-programmed settings in EEPROM (100+ programming cycles)

– Hard Pin Modes: 64 predefined settings in ROM

– Register Default Mode

• Clock frequency margining

– Up to ±50 ppm adjustment of output frequencies via on-board pullable crystal

• Jumper-selectable power options using direct or on-board regulator supplies:

– VDD = 3.3 V

– VDDO = 1.8, 2.5, or 3.3 V

• GUI platform for full access to device registers and EEPROM

• On-board USB-to-I2C programming interface

• LEDs indicators: Loss of Reference and Lock Detection, and USB / I2C activity

6LMK03318EVM User’s Guide SNAU186–November 2015

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Modes of Operation

3 Modes of Operation

The LMK03318 can be configured to start-up in one of three modes upon power-on/reset (POR). The

mode of operation and associated control pins determine which on-chip memory type and memory page

settings are used to initialize the active registers for configuring the Input, PLL, Output, Device Control,

and Status blocks for full operation:

1. Soft Pin Modes (EVM Default) – Loads all registers with one of the 6 page settings stored in

EEPROM. In the EVM-default EEPROM image, all 6 EEPROM pages have pre-programmed register

settings to demonstrate the various clock configurations in Soft Pin Mode using the default EVM

hardware. The EEPROM settings can be easily re-programmed by the user through the GUI platform.

2. Hard Pin Modes – Loads all registers from one of the 64 page settings stored in ROM. All 64 ROM

pages are “hard-coded” with predefined register settings by TI.

NOTE: Refer to the ROM page configurations for Hard Pin Mode in the LMK03318 datasheet. Some

ROM page settings may not operate with the default EVM configuration, and modification of

the EVM may be necessary to operate the intended mode. EVM modification areas may

include the crystal (Y1), PRIREF / SECREF input interfaces, OUT / STATUS output

interfaces, and PLL loop filter C2 capacitor selection (switch S1).

3. Register Default Mode – Loads all registers from the register default setting. The Register Default

Mode is hard-coded with predefined settings.

NOTE: Refer to the Register Default Mode in the LMK03318 datasheet. The Register Default Mode

will NOT operate using the on-board 50 MHz crystal (Y1) as the device expects a 25 MHz

reference input. To operate in Register Default Mode using a crystal input, Y1 must be

changed to a 25-MHz, 9-pF crystal (example P/N: TXC 7M25072001).

Once the LMK03318 is start-up in any of these modes, the I2C interface is enabled to provide (optional)

access to all device registers for full control of the LMK03318 settings. For convenience, a USB-to-I2C

interface is integrated on-board and can be controlled by the GUI platform.

4 Configuring the EVM

The LMK03318 is a highly-configurable clock generator with multiple power domains and input & output

clock domains. To support a wide range of evaluation use cases, the EVM was designed for maximum

flexibility so it has more functionality and peripheral circuitry than needed to implement the clock solution

in a typical customer system application.

This section describes the jumpers and connectors on the EVM, as well as how to connect, set-up, and

use the LMK03318EVM. When operating the LMK03318EVM, the power supply, clock inputs, and clock

outputs can be connected to the SMA ports shown in Figure 2. These SMA ports are labeled in the top

silkscreen layer.

SNAU186–November 2015 LMK03318EVM User’s Guide

Configuring the EVM

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Figure 2. Power, Input, and Output Connections

8LMK03318EVM User’s Guide SNAU186–November 2015

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Configuring the EVM

4.1 Configuring the Power Supply

The LMK03318 has four VDD (analog/digital core) supply pins that operate from 3.3V (+/- 5%) and six

VDDO (output) supply pins that operate from 1.8V to 3.3V (+/- 5%). The VDD and VDDO power planes on

the EVM can be powered from a single supply (3.3 V) or dual supplies (3.3 V and 1.8/2.5/3.3 V). Each

plane can be powered directly from an external supply or an on-board LDO regulator. Though the

LMK03318 already has integrated LDO regulators for excellent power-supply-ripple-rejection (PSRR), the

EVM’s on-board regulators (U3 & U4) allows the user to power the EVM using a higher supply voltage

(like 5 V) and enable jumper selection of the VDDO voltage. The direct external supplies or on-board

regulator supplies can be independently routed for the VDD and VDDO planes by configuring the power

terminals and jumpers shown in Figure 3.

J3 (PWR) is the main power terminal block for the EVM for connecting power and GND leads from an

external power supply. Power SMA ports EXTVDD (J1) and EXTVDDO (J3) provide an alternative

connector style to apply power using coax cables.

NOTE: Some power connections may NOT be used or required to operate the EVM.

Figure 3. Power Terminals and Jumpers

SNAU186–November 2015 LMK03318EVM User’s Guide

Configuring the EVM

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Table 2 summarizes the EVM power configurations to connect and route power to the VDD and VDDO

supply domains of the LMK03318. Refer to Section 7 for more details.

Table 2. Power Configurations

On-board Regulators

CONNECTION NAME Direct Single Supply Direct Dual Supply

(Default)

LMK03318 VDD[x] 3.3 V 3.3 V 3.3 V

VDD pins

LMK03318 VDDO[x] 1.8 / 2.5 / 3.3 V 3.3 V 1.8 / 2.5 / 3.3 V

VDDO pins

J1 EXTVDD Alternative SMA power connection to J3 pins 1 & 3

J2 EXTVDDO Alternative SMA power connection to J3 pins 2 & 3

-Pin 1 (EXTVDD): Connect to

-Pin 1 (EXTVDD): Connect to -Pin 1 (EXTVDD): Connect to 3.3-V supply

5-V supply 3.3-V supply -Pin 2 (EXTVDDO): Connect to

J3 PWR -Pin 2: N/A -Pin 2: N/A 1.8 / 2.5 / 3.3 V supply

-Pin 3 (GND): Connect to GND -Pin 3 (GND): Connect to GND -Pin 3 (GND): Connect to GND

supply supply supply

Tie pins 2-3:

JP1(1) LDOIN Selects 5 V from EXTVDD to N/A N/A

operate regulators Tie pins 2-3: Tie pins 2-3:

Tie pins 1-2:

JP2 VDD Selects 3.3 V directly from Selects 3.3 V directly from

Selects VDD = 3.3 V from U3 EXTVDD EXTVDD

Tie pins 1-2: Tie pins 2-3:

Tie pins 2-4:

JP3 & J4(2) VDDO Selects VDDO = 1.8 / 2.5 / 3.3 Selects 1.8 / 2.5 / 3.3 V

Selects 3.3 V from VDD

V from U4 directly from EXTVDDO

-Open (JP8 Default):

Selects VDDO = 1.8 V

-Tie pins 1-2:

JP8 LDOSEL (U4) N/A N/A

Selects VDDO = 3.3 V

-Tie pins 2-3:

Selects VDDO = 2.5 V

(1) In typical configurations, the LMK03318EVM can consume more current than USB 2.0 limit of 0.5 A. Thus, it is advised to not

use the USB5V rail to power the on-board LDO regulators (i.e. do not tie pins 1-2 on JP1) unless the LMK03318 configuration

and peripheral circuitry are assured to never exceed 0.5 A current limit imposed by the TPS2553 USB switch (U10). The

LMK03318 may not initialize or operate properly when current limited.

(2) JP3 and J4 form a 3-way header where J4 is pin 4.

10 LMK03318EVM User’s Guide SNAU186–November 2015

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