Xilinx MicroBlaze Manuale utente

MicroBlaze

Processor Reference

Guide

2016.1

UG984 (v2016.1) April 6, 2016

UG984 (v2016.2) June 8, 2016

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Revision History

The following table shows the revision history for this document.

Date Version Revision

03/20/2013 2013.1 Initial Xilinx release. This User Guide is derived from UG081.

06/19/2013 2013.2 Updated for Vivado 2013.2 release.

10/02/2013 2013.3 Updated for Vivado 2013.3 release.

12/18/2013 2013.4 Updated for Vivado 2013.4 release.

04/02/2014 2014.1 Updated for Vivado 2014.1 release:

• Added v9.3 to MicroBlaze release version code in PVR.

• Clarified availability and behavior of stack protection registers.

• Corrected description of LMB instruction and data bus exception.

• Included description of extended debug features, new in version 9.3:

performance monitoring, program trace and non-intrusive profiling.

• Included definition of Reset Mode signals, new in version 9.3.

• Clarified how the AXI4-Stream TLAST signal is handled.

• Added UltraScale and updated performance and resource utilization for 2014.1.

10/01/2014 2014.3 Updated for Vivado 2014.3 release:

• Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1.

• Added version 9.4 to MicroBlaze release version code in PVR.

• Included description of external program trace, new in version 9.4

04/15/2015 2015.1 Updated for Vivado 2015.1 release:

• Included description of 16 word cache line length, new in version 9.5.

• Added version 9.5 to MicroBlaze release version code in PVR.

• Corrected description of supported endianness and parameter C_ENDIANNESS.

• Corrected description of outstanding reads for instruction and data cache.

• Updated FPGA configuration memory protection document reference [Ref 10].

• Corrected Bus Index Range definitions for Lockstep Comparison in Table 3-13.

• Clarified registers altered for IDIV instruction.

• Corrected PVR assembler mnemonics for MFS instruction.

• Updated performance and resource utilization for 2015.1.

• Added references to training resources.

04/06/2016 2016.1 Updated for Vivado 2016.1 release:

• Included description of address extension, new in version 9.6.

• Included description of pipeline pause functionality, new in version 9.6

• Included description of non-secure AXI access support, new in version 9.6.

• Included description of hibernate and suspend instructions, new in version 9.6.

• Added version 9.6 to MicroBlaze release version code in PVR.

• Corrected references to Table 2-45 and Table 2-46.

• Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD)

with Xilinx System Debugger (XSDB).

• Removed C code function attributes svc_handler and svc_table_handler.

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Table of Contents

Chapter 1: Introduction

Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2: MicroBlaze Architecture

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Data Types and Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Pipeline Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Privileged Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Virtual-Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Reset, Interrupts, Exceptions, and Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Stream Link Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Debug and Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Fault Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Lockstep Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Data Address Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 3: MicroBlaze Signal Interface Description

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

AXI4 and ACE Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Local Memory Bus (LMB) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Lockstep Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Debug Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Trace Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

MicroBlaze Core Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

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Chapter 4: MicroBlaze Application Binary Interface

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Register Usage Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Stack Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Interrupt, Break and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Chapter 5: MicroBlaze Instruction Set Architecture

Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Appendix A: Performance and Resource Utilization

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Appendix B: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

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Chapter 1

Introduction

The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft

processor, MicroBlaze, which is included in the Vivado® release. The document is intended

as a guide to the MicroBlaze hardware architecture.

Guide Contents

This guide contains the following chapters:

•Chapter 2, MicroBlaze Architecture, contains an overview of MicroBlaze features as well

as information on Big-Endian and Little-Endian bit-reversed format, 32-bit general

purpose registers, cache software support, and Fast Simplex Link interfaces.

•Chapter 3, MicroBlaze Signal Interface Description, describes the types of signal

interfaces that can be used to connect MicroBlaze.

•Chapter 4, MicroBlaze Application Binary Interface, describes the Application Binary

Interface important for developing software in assembly language for the soft

processor.

•Chapter 5, MicroBlaze Instruction Set Architecture, provides notation, formats, and

instructions for the Instruction Set Architecture of MicroBlaze.

•Appendix A, Performance and Resource Utilization, contains maximum frequencies and

resource utilization numbers for different configurations.

•Appendix B, Additional Resources and Legal Notices, provides links to documentation

and additional resources.

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Chapter 2

MicroBlaze Architecture

This chapter contains an overview of MicroBlaze™ features and detailed information on

MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit

general purpose registers, virtual-memory management, cache software support, and

AXI4-Stream interfaces.

Overview

The MicroBlaze™ embedded processor soft core is a reduced instruction set computer

(RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs).

Figure 2-1 shows a functional block diagram of the MicroBlaze core.

Figure 2-1: MicroBlaze Core Block Diagram

Data-sideInstruction-side

ILMB

bus interface bus interface

Instruction

Buffer

Program

Counter

32 X 32b

ALU

Instruction

Decode

Bus

I-Cache

D-Cache

Shift

Barrel Shift

Multiplier

Divider

FPU

Special

Purpose

Registers

Optional MicroBlaze feature

M_AXI_IP

UTLB

ITLB

DTLB

Memory Management Unit (MMU)

M_AXI_IC M_AXI_DC

Branch

Target

Cache

M0_AXIS..

S0_AXIS..

M15_AXIS

S15_AXIS

M_ACE_DC

M_ACE_IC

M_AXI_DP

DLMB

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Chapter 2: MicroBlaze Architecture

Features

The MicroBlaze soft core processor is highly configurable, allowing you to select a specific

set of features required by your design.

The fixed feature set of the processor includes:

• Thirty-two 32-bit general purpose registers

• 32-bit instruction word with three operands and two addressing modes

• Default 32-bit address bus, extensible to 64 bits on the data side

• Single issue pipeline

In addition to these fixed features, the MicroBlaze processor is parameterized to allow

selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze

support a subset of the optional features described in this manual. Only the latest

(preferred) version of MicroBlaze (v9.6) supports all options.

Xilinx recommends that all new designs use the latest preferred version of the MicroBlaze

processor.

Table 2-1, page 7 provides an overview of the configurable features by MicroBlaze versions.

Table 2-1: Configurable Feature Overview by MicroBlaze Version

Feature MicroBlaze versions

v9.1 v9.2 v9.3 v9.4 v9.5 v9.6

Version Status deprecated deprecated deprecated deprecated deprecated preferred

Processor pipeline depth 3/5 3/5 3/5 3/5 3/5 3/5

Local Memory Bus (LMB) data side

interface

option option option option option option

Local Memory Bus (LMB) instruction

side interface

option option option option option option

Hardware barrel shifter option option option option option option

Hardware divider option option option option option option

Hardware debug logic option option option option option option

Stream link interfaces 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI

Machine status set and clear

instructions

option option option option option option

Cache line word length 4, 8 4, 8 4, 8 4, 8 4, 8, 16 4, 8, 16

Hardware exception support option option option option option option

Pattern compare instructions option option option option option option

Floating point unit (FPU) option option option option option option

Disable hardware multiplier1option option option option option option

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Chapter 2: MicroBlaze Architecture

Hardware debug readable ESR and

EAR

Yes Yes Yes Yes Yes Yes

Processor Version Register (PVR) option option option option option option

Area or speed optimized option option option option option option

Hardware multiplier 64-bit result option option option option option option

LUT cache memory option option option option option option

Floating point conversion and square

root instructions

option option option option option option

Memory Management Unit (MMU) option option option option option option

Extended stream instructions option option option option option option

Use Cache Interface for All I-Cache

Memory Accesses

option option option option option option

Use Cache Interface for All D-Cache

Memory Accesses

option option option option option option

Use Write-back Caching Policy for D-

Cache

option option option option option option

Branch Target Cache (BTC) option option option option option option

Streams for I-Cache option option option option option option

Victim handling for I-Cache option option option option option option

Victim handling for D-Cache option option option option option option

AXI4 (M_AXI_DP) data side interface option option option option option option

AXI4 (M_AXI_IP) instruction side

interface

option option option option option option

AXI4 (M_AXI_DC) protocol for D-

Cache

option option option option option option

AXI4 (M_AXI_IC) protocol for I-Cache option option option option option option

AXI4 protocol for stream accesses option option option option option option

Fault tolerant features option option option option option option

Force distributed RAM for cache tags option option option option option option

Configurable cache data widths option option option option option option

Count Leading Zeros instruction option option option option option option

Memory Barrier instruction Yes Yes Yes Yes Yes Yes

Stack overflow and underflow

detection

option option option option option option

Allow stream instructions in user

mode

option option option option option option

Lockstep support option option option option option option

Configurable use of FPGA primitives option option option option option option

Table 2-1: Configurable Feature Overview by MicroBlaze Version

Feature MicroBlaze versions

v9.1 v9.2 v9.3 v9.4 v9.5 v9.6

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Chapter 2: MicroBlaze Architecture

Low-latency interrupt mode option option option option option option

Swap instructions option option option option option option

Sleep mode and sleep instruction Yes Yes Yes Yes Yes Yes

Relocatable base vectors option option option option option option

ACE (M_ACE_DC) protocol for D-

Cache

option option option option option option

ACE (M_ACE_IC) protocol for I-Cache option option option option option option

Extended debug: performance

monitoring, program trace, non-

intrusive profiling

option option option option

Reset mode: enter sleep or debug

halt at reset

option option option option

Extended debug: external program

trace

option option option

Extended data addressing option

Pipeline pause functionality Yes

Hibernate and suspend instructions Yes

Non-secure mode Yes

1. Used for saving DSP48E primitives.

Table 2-1: Configurable Feature Overview by MicroBlaze Version

Feature MicroBlaze versions

v9.1 v9.2 v9.3 v9.4 v9.5 v9.6

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Chapter 2: MicroBlaze Architecture

Data Types and Endianness

MicroBlaze uses Big-Endian or Little-Endian format to represent data, depending on the

selected endianness. The parameter C_ENDIANNESS is fixed to 1 (little-endian).

The hardware supported data types for MicroBlaze are word, half word, and byte. When

using the reversed load and store instructions LHUR, LWR, SHR and SWR, the bytes in the

data are reversed, as indicated by the byte-reversed order.

The bit and byte organization for each type is shown in the following tables.

Table 2-2: Word Data Type

Big-Endian Byte Address nn+1 n+2 n+3

Big-Endian Byte Significance MSByte LSByte

Big-Endian Byte Order nn+1 n+2 n+3

Big-Endian Byte-Reversed Order n+3 n+2 n+1 n

Little-Endian Byte Address n+3 n+2 n+1 n

Little-Endian Byte Significance MSByte LSByte

Little-Endian Byte Order n+3 n+2 n+1 n

Little-Endian Byte-Reversed Order nn+1 n+2 n+3

Bit Label 031

Bit Significance MSBit LSBit

Table 2-3: Half Word Data Type

Big-Endian Byte Address nn+1

Big-Endian Byte Significance MSByte LSByte

Big-Endian Byte Order nn+1

Big-Endian Byte-Reversed Order n+1 n

Little-Endian Byte Address n+1 n

Little-Endian Byte Significance MSByte LSByte

Little-Endian Byte Order n+1 n

Little-Endian Byte-Reversed Order nn+1

Bit Label 0 15

Bit Significance MSBit LSBit

Table 2-4: Byte Data Type

Byte Address n

Bit Label 0 7

Bit Significance MSBit LSBit

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