Alinx ACU2CG Manuale utente

ZYNQ UltraScale+ MPSoC

FPGA SOM Core Board

ACU2CG

User Manual

ACU2CG User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2022-09-08

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Table of Contents

Version Record .............................................................................................2

Part 1: ACU2CG core board ........................................................................ 4

Part 1.1: ACU2CG core board Introduction ......................................... 4

Part 1.2: ZYNQ Chip .............................................................................5

Part 1.3: DDR4 DRAM ..........................................................................7

Part 1.4: QSPI Flash ...........................................................................12

Part 1.5: eMMC Flash .........................................................................13

Part 1.6: Clock configuration .............................................................. 15

Part 1.7: LED ...................................................................................... 17

Part 1.8: Power Supply .......................................................................18

Part 1.9: ACU2CG Core Board Form Factor ..................................... 19

Part 1.10: Board to Board Connectors pin assignment .....................19

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Part 1: ACU2CG core board

Part 1.1: ACU2CG core board Introduction

ACU2CG (core board model, the same below) FPGA core board, ZYNQ

chip is based on XCZU2CG-1SFVC784E of XILINX company Zynq UltraScale+

MPSoCs CG series.

This core board uses 4 Micron DDR4 chips MT40A512M16GE on the PS

side, to form a 64-bit data bus bandwidth and 2GB capacity. The highest

operating speed of DDR4 SDRAM on the PS side can reach 1200MHz (data

rate 2400Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC

FLASH chip are also integrated on the core board to start storage configuration

and system files.

In order to connect with the carrier board, the four board-to-board

connectors of this core board expand the PS side USB2.0 interface, Gigabit

Ethernet interface, SD card interface and other remaining MIO ports; also

expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO

ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the

XCZU2CG chip and the interface has been processed with equal length and

differential, and the core board size is only 3.15*2.36 (inch), which is very

suitable for secondary development.

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Figure 2-1-1: ACU2CG Core Board (Front View)

Part 1.2: ZYNQ Chip

The FPGA core board ACU2CG uses Xilinx's Zynq UltraScale+ MPSoCs

CG series chip, module XCZU2CG-1SFVC784E. The PS system of the

ZU2CG chip integrates 2 ARM Cortex™-A53 processors with a speed of up to

1.2Ghz and supports Level 2 Cache; it also contains 2 Cortex-R5 processors

with a speed of up to 500Mhz

The ZU2CG chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,

LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as

PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0 , Gigabit

Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end

contains a wealth of programmable logic units, DSP and internal RAM.

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Figure 2-2-1:

Overall Block Diagram of the

ZYNQ ZU2CG

Chip

The main parameters of the PS system part are as follows:

ARM quad-core Cortex ™-A53 processor, speed up to 1.2GHz, each

CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,

shared by 2 CPUs

ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU

32KB level 1 instruction and data cache, and 128K tightly coupled

memory.

External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3

interface

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Static storage interface, support NAND, 2xQuad-SPI FLASH.

High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,

Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet

Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,

2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO

Power management: Supports the division of four parts of power

supply Full/Low/PL/Battery.

Encryption algorithm: support RSA, AES and SHA.

System monitoring: 10-bit 1Mbps AD sampling for temperature and

voltage detection.

The main parameters of the PL logic part are as follows:

Logic Cells: 103K

Flip-flops: 94K

Look-up-tables (LUTs): 47K



Block RAM

: 5.3MB

Clock Management Units (CMTs): 3

18x25MACCs: 240

XCZU2CG-1SFVC784E chip speed grade is -1, industrial grade, package

is SFVC784

Part 1.3: DDR4 DRAM

The ACU2CG core board is equipped with 4 Micron (Micron) 512MB

DDR4 chips, model is PANGO CXDQ2BFAM-CG (Compatible with

MT40A256M16GE-083E), to form a 64-bit data bus bandwidth and 2GB

capacity. The maximum operating speed of the DDR4 SDRAM on the PS side

can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems

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are directly connected to the memory interface of the PS BANK504. The

highest operating speed of the DDR4 SDRAM on the PL side can reach

1066MHz (data rate 2133Mbps), and four DDR4 storage systems are directly

connected to the memory interface of PS's BANK504. The specific

configuration of DDR4 SDRAM is shown in Table 2-3-1 below:

Bit Number

Chip Model

Capacity

Factory

U12,U14,U15,U16

CXDQ2BFAM-CG

256M x 16bit

PANGO

Table 2-3-1: DDR4 SDRAM Configuration

The hardware design of DDR4 requires strict consideration of signal

integrity. We have fully considered the matching resistor/terminal resistance,

trace impedance control, and trace length control in circuit design and PCB

design to ensure high-speed and stable operation of DDR4.

The hardware connection of DDR4 SDRAM on the PS Side is shown in

Figure 2-3-1:

Figure 2-3-1: DDR4 DRAM schematic diagram on the PS Side

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PS Side DDR4 DRAM pin assignment:

Signal Name

Pin Name

Pin Number

PS_DDR4_DQS0_P

PS_DDR_DQS_P0_504

AF21

PS_DDR4_DQS0_N

PS_DDR_DQS_N0_504

AG21

PS_DDR4_DQS1_P

PS_DDR_DQS_P1_504

AF23

PS_DDR4_DQS1_N

PS_DDR_DQS_N1_504

AG23

PS_DDR4_DQS2_P

PS_DDR_DQS_P2_504

AF25

PS_DDR4_DQS2_N

PS_DDR_DQS_N2_504

AF26

PS_DDR4_DQS3_P

PS_DDR_DQS_P3_504

AE27

PS_DDR4_DQS3_N

PS_DDR_DQS_N3_504

AF27

PS_DDR4_DQS4_P

PS_DDR_DQS_P4_504

N23

PS_DDR4_DQS4_N

PS_DDR_DQS_N4_504

M23

PS_DDR4_DQS5_P

PS_DDR_DQS_P5_504

L23

PS_DDR4_DQS5_N

PS_DDR_DQS_N5_504

K23

PS_DDR4_DQS6_P

PS_DDR_DQS_P6_504

N26

PS_DDR4_DQS6_N

PS_DDR_DQS_N6_504

N27

PS_DDR4_DQS7_P

PS_DDR_DQS_P7_504

J26

PS_DDR4_DQS7_N

PS_DDR_DQS_N7_504

J27

PS_DDR4_DQ0

PS_DDR_DQ0_504

AD21

PS_DDR4_DQ1

PS_DDR_DQ1_504

AE20

PS_DDR4_DQ2

PS_DDR_DQ2_504

AD20

PS_DDR4_DQ3

PS_DDR_DQ3_504

AF20

PS_DDR4_DQ4

PS_DDR_DQ4_504

AH21

PS_DDR4_DQ5

PS_DDR_DQ5_504

AH20

PS_DDR4_DQ6

PS_DDR_DQ6_504

AH19

PS_DDR4_DQ7

PS_DDR_DQ7_504

AG19

PS_DDR4_DQ8

PS_DDR_DQ8_504

AF22

PS_DDR4_DQ9

PS_DDR_DQ9_504

AH22

PS_DDR4_DQ10

PS_DDR_DQ10_504

AE22

PS_DDR4_DQ11

PS_DDR_DQ11_504

AD22

PS_DDR4_DQ12

PS_DDR_DQ12_504

AH23

PS_DDR4_DQ13

PS_DDR_DQ13_504

AH24

PS_DDR4_DQ14

PS_DDR_DQ14_504

AE24

PS_DDR4_DQ15

PS_DDR_DQ15_504

AG24

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PS_DDR4_DQ16

PS_DDR_DQ16_504

AC26

PS_DDR4_DQ17

PS_DDR_DQ17_504

AD26

PS_DDR4_DQ18

PS_DDR_DQ18_504

AD25

PS_DDR4_DQ19

PS_DDR_DQ19_504

AD24

PS_DDR4_DQ20

PS_DDR_DQ20_504

AG26

PS_DDR4_DQ21

PS_DDR_DQ21_504

AH25

PS_DDR4_DQ22

PS_DDR_DQ22_504

AH26

PS_DDR4_DQ23

PS_DDR_DQ23_504

AG25

PS_DDR4_DQ24

PS_DDR_DQ24_504

AH27

PS_DDR4_DQ25

PS_DDR_DQ25_504

AH28

PS_DDR4_DQ26

PS_DDR_DQ26_504

AF28

PS_DDR4_DQ27

PS_DDR_DQ27_504

AG28

PS_DDR4_DQ28

PS_DDR_DQ28_504

AC27

PS_DDR4_DQ29

PS_DDR_DQ29_504

AD27

PS_DDR4_DQ30

PS_DDR_DQ30_504

AD28

PS_DDR4_DQ31

PS_DDR_DQ31_504

AC28

PS_DDR4_DQ32

PS_DDR_DQ32_504

T22

PS_DDR4_DQ33

PS_DDR_DQ33_504

R22

PS_DDR4_DQ34

PS_DDR_DQ34_504

P22

PS_DDR4_DQ35

PS_DDR_DQ35_504

N22

PS_DDR4_DQ36

PS_DDR_DQ36_504

T23

PS_DDR4_DQ37

PS_DDR_DQ37_504

P24

PS_DDR4_DQ38

PS_DDR_DQ38_504

R24

PS_DDR4_DQ39

PS_DDR_DQ39_504

N24

PS_DDR4_DQ40

PS_DDR_DQ40_504

H24

PS_DDR4_DQ41

PS_DDR_DQ41_504

J24

PS_DDR4_DQ42

PS_DDR_DQ42_504

M24

PS_DDR4_DQ43

PS_DDR_DQ43_504

K24

PS_DDR4_DQ44

PS_DDR_DQ44_504

J22

PS_DDR4_DQ45

PS_DDR_DQ45_504

H22

PS_DDR4_DQ46

PS_DDR_DQ46_504

K22

PS_DDR4_DQ47

PS_DDR_DQ47_504

L22

PS_DDR4_DQ48

PS_DDR_DQ48_504

M25

PS_DDR4_DQ49

PS_DDR_DQ49_504

M26

PS_DDR4_DQ50

PS_DDR_DQ50_504

L25

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