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3.1 JTAG
First of all ,we talk about FPGA configuration and debugging interface: JTAG interface.
The function of the JTAG interface is to download the compiled program (.sof) to the
FPGA or download the FLASH configuration program (.jic) to the SPI FLASH.After the
sof file is downloaded to the FPGA, it will be lost after power-off ,so we need to download
it again after the power-on. At this time, we can use the Quartus software to convert the sof
file into a jic file.After downloading the jic file to the development board's FLASH via
JTAG, it will not be lost after power-off. After the power-on, the FPGA will read the jic
configuration file in the FLASH and run.
Figure 3-2 shows the schematic part of the JTAG port, which involves the four signals
TCK, TDO, TMS, and TDI. These four signals are directly derived from the FPGA pins.
Each signal has a diode overvoltage protection circuit on the development board.
Figure 3-2
3.2 Power and GND
The power supply pin portion of the FPGAincludes each bank's power pin, core voltage pin,
analog voltage, and phase-locked loop power supply pin. VCCINT is the FPGA core power
supply pin, which is connected to 1.2V; VCCIO is for each BANK of the FPGA. Power
supply voltage, where VCCIO0 is the power supply pin of the BANK0 of the FPGA.
Similarly, VCCIO1~VCCIO3 are power supply pins of the BANK~BANK3 of the FPGA
respectively. In the development board, VCCIO is connected to 3.3V voltage, that is to say,
this The development board FPGA pins are 3.3V inputs and outputs. VCCA is the FPGA
analog supply pin, followed by 2.5V, VCCD_PLL is the FPGAPLL power supply pin, also
connected to 1.2V, FPGA power supply connection diagram shown in Figure 3-3.
