Analog Devices EV-ADF4355SD1Z Manuale utente

EV-ADF4355SD1Z User Guide

UG-805

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADF4355 Microwave Wideband Synthesizer with Integrated VCO

FEATURES

Self contained board, including ADF4355 frequency

synthesizer with integrated VCO, differential 122.88 MHz

temperature controlled crystal oscillator (TCXO), loop

filter (20 kHz), USB interface, and voltage regulators

Windows®-based software allows control of synthesizer

functions from a PC

Externally powered by 6 V

EVALUATION KIT CONTENTS

EV-ADF4355SD1Z

USB cable

EQUIPMENT NEEDED

Windows-based PC with USB port for evaluation software

System demonstration platform, serial only (SDP-S)

EVAL-SDP-CS1Z controller board

Power supply (6 V)

Spectrum analyzer

50 Ω terminators

ONLINE RESOURCES

Documents Needed

ADF4355 data sheet

EV-ADF4355SD1Z user guide

PLL Software Installation Guide

Required Software

Analog Devices, Inc., ADF4355 software, Version 0.46.1 or

higher (available for download at

www.analog.com/ADF4355)

GENERAL DESCRIPTION

The EV-ADF4355SD1Z evaluates the performance of the

ADF4355 frequency synthesizer with integrated VCO for

phase-locked loops (PLLs). A photograph of the evaluation

board is shown in Figure 1. The evaluation board contains

the ADF4355 frequency synthesizer with integrated VCO, a

differential 122.88 MHz reference (TCXO), a loop filter, a

USB interface, power supply connectors, and subminiature

Version A (SMA) connectors. A USB cable is included to

connect the board to a PC USB port.

For easy programming of the synthesizer, download the

Windows-based software from www.analog.com/ADF4355.

This board requires an SDP-S (shown in Figure 1, but not

supplied with the kit). The SDP-S allows software programming

of the EV-ADF4355SD1Z device.

EVALUATION BOARD PHOTOGRAPH

Figure 1. EV-ADF4355SD1Z

12944-001

UG-805 EV-ADF4355SD1Z User Guide

Rev. 0 | Page 2 of 18

TABLE OF CONTENTS

Features .............................................................................................. 1

Evaluation Kit Contents................................................................... 1

Equipment Needed........................................................................... 1

Online Resources.............................................................................. 1

General Description ......................................................................... 1

Evaluation Board Photograph......................................................... 1

Revision History ............................................................................... 2

Getting Started .................................................................................. 3

Software Installation Procedures................................................ 3

Evaluation Board Setup Procedures........................................... 3

Evaluation Board Hardware............................................................ 4

Power Supplies .............................................................................. 4

RF Output.......................................................................................4

Loop Filter......................................................................................4

Reference Source ...........................................................................4

Default Configuration ..................................................................4

Evaluation Board Setup ................................................................5

Evaluation Board Software...............................................................6

Main Controls................................................................................6

Evaluation and Test ...........................................................................7

Evaluation Board Schematics and Artwork...................................8

Ordering Information.................................................................... 17

Bill of Materials........................................................................... 17

REVISION HISTORY

5/15—Revision 0: Initial Version

EV-ADF4355SD1Z User Guide UG-805

GETTING STARTED

SOFTWARE INSTALLATION PROCEDURES

See the ADF4355 product page for the EV-ADF4355SD1Z

control software. For the software installation procedure, see

the PLL Software Installation Guide.

EVALUATION BOARD SETUP PROCEDURES

To run the sof tware,

1. Click the ADF4355 file on the desktop or from the Start

menu.

2. On the Select Device and Connection tab, choose

ADF4355 and SDP board (black), and then click Connect

(see Figure 2).

3. When connecting the board, allow 5 sec to 10 sec for the

label on the status bar to change.

Under the File menu, the current settings can be saved to, and

loaded from, a text file.

Figure 2. Software Front Panel Display—Select Device and Connection

12944-002

UG-805 EV-ADF4355SD1Z User Guide

Rev. 0 | Page 4 of 18

EVALUATION BOARD HARDWARE

The EV-ADF4355SD1Z requires the SDP-S platform that uses

the E VA L-SDP-CS1Z. (SDP-B is not recommended.)

The EV-ADF4355SD1Z schematics are shown in Figure 7,

Figure 8, and Figure 9. The silkscreens for the evaluation board

are shown in Figure 10 and Figure 11.

POWER SUPPLIES

The board is powered by a 6 V power supply connected to the

red and black banana connectors. Connect the red connector to

a 6 V power supply and the black connector to ground.

The power supply circuitry allows the user two or three separate

low dropout (LDO) regulators to feed the ADF4355 (using

fewer LDO regulators increases the risk of spur contaminated

dc feeds).

The charge pump and VCO supply pins are driven from a

5 V ADM7150 high performance, low noise regulator. The

remaining supplies are powered from 3.3 V ADM7150 high

performance, low noise regulator.

LED1 indicates when the ADF4355 is powered on. Use

Switch S1 to switch the 6 V to the board on and off.

RF OUTPUT

The EV-ADF4355SD1Z has two pairs of SMA output

connectors: RFOUTA+/RFOUTA− and RFOUTB+/RFOUTB−

(differential outputs). Because they are sensitive to impedance

mismatch, connect the RF outputs to equal load impedances.

If only one port of a differential pair is used, terminate the

complementary port with an equal load terminator (in general,

a 50 Ω terminator).

LOOP FILTER

The loop filter schematic is included in the board schematic in

Figure 7. Figure 3 shows the loop filter component placements.

For lowest rms phase noise, use the following components (that

are inserted on the evaluation board) with a 0.9 mA charge

pump current:

•C60 = 1.2 nF, C59 = 33 nF, C6 1 = 390 pF, C73 = 10 pF

•R14 = 1 kΩ, R17 = 3.3 kΩ

Narrower loop filter bandwidths have lower spurious signals.

Figure 3. Loop Filter Placement

REFERENCE SOURCE

The evaluation board contains a 122.88 MHz differential output

TCXO from Vectron International. If preferred, the user may

supply either a single-ended or differential reference input to

REFINA/REFINB SMA connectors. When using an external

reference, remove R12 to disconnect the power rail to the

TCXO.

To use a single-ended REFINx, connect a low noise 122.88 MHz

reference source to SMA REFINB, and connect a 50 Ω terminator

to SMA REFINA. Remove Resistor R27 (100 Ω). To use a

differential REFINx, connect the differential signal to SMA

REFINA and SMA REFINB. The differential REFINA/REFINB

SMA connectors can operate to a 500 MHz input frequency.

In the schematic shown in Figure 7, the REFINA pin of U1

(ADF4355) is connected to SMA REFINB, and the REFINB pin

of U1 (ADF4355) is connected to SMA REFINA. This

schematic matches the evaluation board connections.

DEFAULT CONFIGURATION

All components necessary for local oscillator (LO) generation

are inserted on the board. This board is shipped with the

ADF4355 synthesizer with an integrated VCO, a differential

122.88 MHz reference TCXO, and a 20 kHz loop filter (ICP =

0.9 mA).

RVTUNE

C73

RCPOUT

R17

RPIN18

C60

C59

R14

C61

12944-003

EV-ADF4355SD1Z User Guide UG-805

EVALUATION BOARD SETUP

Figure 4. Evaluation Setup Block Diagram

SPECTRUM

ANALYZER

EXTERNAL DC

SUPPLY

TCXO

ADF4355

LOOP FILTER

LOCK

DETECT

LED

PLL

POWER

LED

EXTERNAL POWER

SWITCH

REFERENCE

IN/OUT

SDP-S BOARD

REFINA

REFINB

RFOUTA–

RFOUTB–

RFOUTA+

RFOUTB+

VSUPPLY

REFERENCE

(OPTIONAL)

SIGNAL GENERATOR

(UNDERNEATH BOARD)

EXTERNAL DC

GND

USB

12944-004

UG-805 EV-ADF4355SD1Z User Guide

Rev. 0 | Page 6 of 18

EVALUATION BOARD SOFTWARE

MAIN CONTROLS

The Main Controls tab (see Figure 5) selects the RF and user

configurable register settings. Consult the register descriptions

of the ADF4355 data sheet for details. Default settings are

recommended for most registers.

In the RF Settings, ensure that VCOout (MHz) equals the

VCO frequency. Set the Output divider to give the required

RFoutA± (MHz).

Ensure that Reference freq equals the applied reference signal.

The PFD frequency is calculated from the reference frequency,

the R counter, the reference doubler, and the reference divide

by 2. Ensure that the value in PFD (MHz) matches the value

specified in the loop filter design.

In Register 4, program the CP current to match the value used

for the loop filter design.

Figure 5. Software Front Panel Display—Main Controls

12944-005

EV-ADF4355SD1Z User Guide UG-805

EVALUATION AND TEST

To evaluate and test the performance of the ADF4355, use the

following procedure:

1. Install the ADF4355 software (see the PLL Software

Installation Guide).

2. Follow the hardware driver installation procedure

(Windows XP only).

3. Connect a 50 Ω terminator to RFOUTA−.

4. Connect the EV-ADF4355SD1Z board to the SDP-S board.

5. Connect the 6 V power supply to the banana connectors

and power-on the board using S1 (check that LED1 is on).

6. Connect the USB cable from the SDP-S board to the PC.

7. Run the ADF4355 software.

8. Select ADF4355 and SDP board (black) in the Select

Device and Connection tab of the software front panel

display window (see Figure 2).

9. Click the Main Controls tab, and set the VCOout (MHz)

to a frequency of 5000 MHz.

10. Click Write Al l Registers.

11. Connect the spectrum analyzer to SMA connector

RFOUTA+, see Figure 4 for a typical evaluation setup.

12. Measure the output spectrum and single sideband phase

noise.

Figure 6 shows a phase noise plot of the SMA RFOUTA+ equal

to 5 GHz.

Figure 6. Single Sideband Phase Noise

–160

–170

–120

–130

–150

–140

–80

–

–90

–100

–110

1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

PHASE NOISE (dBc/Hz)

–160

–170

–120

–130

–150

–140

–80

–

–90

–100

–110

SPUR POWER (dBc)

12944-006

UG-805 EV-ADF4355SD1Z User Guide

Rev. 0 | Page 8 of 18

EVALUATION BOARD SCHEMATICS AND ARTWORK

Figure 7. Evaluation Board Schematic—Page 1

ADF4355

REFINA AND REFINB ARE SPACED 15mm

CENTER TOCENTER ON PCB

125MHz

DNI

Y1_ALT

5.1kΩ

C41

1000pF

C39

1000pF

RA3

0Ω

DNI

TP1

TP2

REFINB

2 3

5 4

45 3 2

+3.3V

GND VDD

CFO

GND

E/D

GND

PAD

CREG2

SDGND

MUXOUT

REFINA

REFINB

DVDD

PDBRF

CREG1

VBIAS

VREF

RSET

AGNDVCO

VTUNE

VREGVCO

AGNDVCO

VVCO

AVDD

RFOUTB+

RFOUTB–

AGNDRF

RFOUTA–

RFOUTA+

VREF

AGND

CPGND

CPOUT

AVDD

DATA

CLK

GND

VCC

OUT–

OUT+

C2 GND

VTUNE

GND

122.88MHz

TP6

CLK

DATA

GND GND GND

TP5TP4TP3

R18

1.8kΩ R19

1.8kΩ R23

1.8kΩ

R24

DNI R25

1.5kΩ

LOOP FILTER

PLACE ON BOTTOM SIDE

OFPCB SHIELD SIGNALS WITH VIAS

RF CHOKE

MATED LINE WIDTH’S

TRACE WIDTH = 380µm

LOCK DETECT

RMUX

0Ω R22

68Ω

MUXOUT

R20

0Ω

DNI

DS1

R26

0Ω

DNI

CREG1

VP MUXOUT

+3.3V

1AC

GND

R12

0Ω

C35

0.1µF

GND

C25

10pF

GND

C53

0.1µF GND

C48

10pF

+3.3V

GND

C44

100pF GND

C47

1µF DVDD

GND

C33

0.1µF GND

C37

10pF

AVDD2

GND

C45

0.1µF GND

C43

10pF

REFINA

45 3 2

GND GND

C50

0.1µF GND

C46

10pF

VRF

GNDGND

C36

1000pF

GND

C38

10pF

VVCO

GND

C12

1µF

GND

C32

1000pF

GND

C34

10pF

CPOUT

GND

C73

10pF

DNI

GND

C61

390pF

GND

C60

1600pF

VTUNE

GND

C59

0.033µF

R14

1kΩ

0Ω

R17

3.3kΩ

RCPOUT

0Ω

GND

C55

0.1µF

GND

C54

10pF

AVDD1

R21

0Ω C23

DNI

GND R4

0Ω

GND

C17

4.7µF

GND

C27

1000pF

GND

C29

10pF

VREF

GND

C19

10µF

GND

C30

1000pF

GND

C31

10pF

GND

C15

1µF

DNI

GND

C26

0.1µF

GND

C28

10pF

VBIAS

VREGVCO

ADF4355

+3.3V

PAD

GND

0Ω

DNI

10kΩ

PDRF

32K243-40ML5

RFOUTA+

GND

10pF

0201

GND

VRF1

7.4nH

0302

4.7nH

0201

DNI

R32

0Ω

0201

RFOUTA–

GND

10pF

0201

GND

VRF1

7.4nH

0302

4.7nH

0201

DNI

R33

0Ω

0201

32K243-40ML5

RFOUTB+

GND

C64

100pF

0201

GND

VRF1

100nH

0402

4.7nH

0201

DNI

R34

0Ω

0201

32K243-40ML5

RFOUTB–

GND

C63

100pF

0201

GND

VRF1

100nH

0402

4.7nH

0201

DNI

R35

0Ω

0201

C56

120pF

C21

1µF

C57

120pF

C58

0.1µF

VRF1

GND

C65

120pF

C66

1µF

C68

120pF

C67

0.1µF

VRF1

CREG2

51Ω

DNI +3.3V

R10

51Ω

DNI

51Ω

DNI

51Ω

DNI

R16

0Ω

R11

0Ω

RA5

0Ω

DNI

RA4

0Ω

DNI

R27

100Ω

C42

1000pF

C40

1000pF

+3.3V

CA5

1µF

DNI

CA4

1µF

DNI

CA3

1µF

DNI

GND

CA2

1µF

DNI

GND

CA1

100pF

DNI

RA2

0Ω

DNI

RA1

0Ω

DNI

GND

12944-007

EV-ADF4355SD1Z User Guide UG-805

Figure 8. Evaluation Board Schematic—Page 2

JUMPER 3 PIN

PLACE VBIAS, VREF 7 VREGVCO

RESISTORS CLOSE TO DUT PINS

DNI

10µF

R_VBIAS

TP_VP

CVP

22µF

RV1

VSUPPLY

C71

22µF

C74

100µF

VSUPPLY

MUX/LE

VREGVCO

VBIAS

VREF

35 4 3 2

GND

ADM7150ACPZ-5.0

VR2

PAD

VIN

REF

REF_SENSE

GND

BYP

VOUT

VREG

GND GND

AVDD

DVDD

VRF

VRF1

VVCO

VRVCO

GND

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

G27

G28

G29

G30

G31

G32

G33

G34

G35

G36

8IN

G10

G11

G12

G13

G14

G15

G16

CPOUT

VTUNE

RVTUNE

0Ω

DNI

RPIN18

0Ω

DNI

PLACE VTUNE, CPOUT AND SW

RESISTORS CLOSE TO DUT PINS

SHIELD SIGNALS WITH VIAS ALL

THE WAY TO THE DUT PINS.

MUX/LE

MUXOUT

GND VSUPPLY_ALT

ZD1

0Ω

TP_+3.3V

R3V3

1kΩ

RAVDD GND

LED1

3.3V

AVDD2

TP_AVDD2

AVDD2

0Ω

TP_AVDD1

RV15

0Ω

RV26

0Ω

RV14 AVDD1

0Ω

TP_VVCO

CVVCO

22µF

RV7 VVCO

GND GND

GND

C13

1µF

GND

10µF

GND

1µF

GND

C10

10µF

GND

RV10

0Ω

DNI

RV9

0Ω

GND

CVRVCO

22µF

GND

RV6

0Ω

RV3

0Ω

RV2

0Ω

DNI

RV30

0Ω

RV4

DNI

RV19

0Ω

RV12

0Ω

RV8

0Ω

DNI

R_VREF

DNI

R_VREGVCO

0Ω

RV11

0Ω 6V

C75

100µF

VR3

PAD

VIN

REF

REF_SENSE

GND

BYP

VOUT

VREG

C14

1µF

GND

10µF

GND

1µF

10µF

GND

C16

10µF

GND

CDVDD

22µF

TP_DVDD

0Ω

RV20 DVDD

GND

CAVDD

22µF

0Ω

RV25 VRF

GND

CVRF

22µF

TP_VRF1

TP_VRF

0Ω

RV31 VRF1

GND

CVRF1

22µF

GND

C11

10µF

GND

RV17

0Ω

DNI

RV5

0Ω

RV16

0Ω

GND

RV18

0Ω 6V

ADM7150ACPZ-3.3

C76

100µF

VR5

PAD

VIN

REF

REF_SENSE

GND

BYP

VOUT

VREG

C24

1µF

GND

C20

10µF

GND

C18

1µF

GND

C22

10µF

GND

RV28

0Ω

DNI

RV27

0Ω

GND

RV29

0Ω 6V

ADM7150ACPZ-3.3

12944-008

UG-805 EV-ADF4355SD1Z User Guide

Rev. 0 | Page 10 of 18

Figure 9. Evaluation Board Schematic—Page 3

24LC32A-I/MS

SDA

SCL

RDATA

1.5kΩ

RLE

1.5kΩ

RE3

TBD0603

DNI

RE2

100kΩ

RE1

100kΩ

UE1

CN1CN1

DATA

CLK

PDRF

MUXOUT

SDA_0

VIO_+3.3V

SCL_0

120

GND

GND GND GND

VSS

VCC

SCL SDA

GNDGND

RMUXOUT

0Ω

RCLK

1.5kΩ

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

R28

0Ω

DNI

R29

0Ω

DNI

R31

0Ω

DNI

R30

0Ω

DNI

12944-009

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