Analog Devices LTC3302A Manuale utente
User Guide | DC3251A
UG-2105
Evaluating the LTC3302A, 3.3 V to 1.2 V at 2 A, 2 MHz Synchronous Step-Down Regulator in a 2 mm × 2 mm SWF FCQFN
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | 1 of 13
FEATURES
►LTC3302A evaluation board
►Transient circuit included for load-transient evaluation
►EMI filter included to reduce noise in EMI emission tests
EVALUATION KIT CONTENTS
►DC3251A evaluation board
DOCUMENTS NEEDED
►LTC3302A data sheet
EQUIPMENT NEEDED
►One 5 V, 2 A, DC power supply
►One 2 A, Electronic load
►Three digital voltmeters
►Two digital ammeters
GENERAL DESCRIPTION
Demonstration Circuit DC3251A features the LTC3302A, 5 V, 2 A
synchronous step-down silent switcher operating as a 2 MHz, 3.3
V to 1.2 V, 2 A buck regulator. The LTC3302A supports adjustable
output voltages from 0.5 V to VIN. The LTC3302A is a compact,
high efficiency, and high-speed synchronous monolithic step-down
switching regulator. A minimum on-time of 27 ns enables high VIN to
low VOUT conversion.
The DC3251A operating mode can be selected as Burst Mode
operation, skip (PS) or forced continuous (FC) mode. Setting JP1
to the SKIP position allows the LTC3302A to sync to a clock
frequency from 1.6 MHz to 2.4 MHz. The LTC3302A operates in
forced continuous mode when syncing to an external clock.
The DC3251A also has an EMI filter to reduce conducted EMI. This
EMI filter can be included by applying the input voltage at the VIN
EMI terminal. The EMI performance of the board is shown in the
EMI Test Results section. The red lines in the EMI performance
graphs show the CISPR25 Class 5 peak limits for the conducted
and radiated emission tests.
The LTC3302A data sheet gives a complete description of the
device, operation, and application information. Full specifications on
the LTC3302A are available in the LTC3302A data sheet available
from Analog Devices, Inc., and must be consulted with this user
guide when using the DC3251A evaluation board. The LTC3302A is
assembled in a 2 mm × 2 mm FCQFN package with side wettable
flanks (SWF) for visual solder inspection. The layout recommenda-
tions for low EMI operation and maximum thermal performance are
available in the data sheet section Low EMI PCB Layout.
Figure 7 shows the efficiency and the power loss of the circuit with
a 3.3 V input in Burst Mode operation.
User Guide DC3251A
TABLE OF CONTENTS
analog.com Rev. 0 | 2 of 13
Features................................................................ 1
Evaluation Kit Contents......................................... 1
Documents Needed...............................................1
Equipment Needed................................................1
General Description...............................................1
DC3251A Evaluation Board Photograph............... 3
Performance Summary..........................................4
Quick Start Procedure........................................... 5
Typical Performance Characteristics..................... 8
EMI Test Results....................................................9
Evaluation Board Hardware.................................10
Introduction to the DC3251A............................10
Accurately Measuring Output Ripple of the
LTC3302A...................................................... 10
Evaluation Board Schematic................................11
Ordering Information............................................12
Bill of Materials.................................................12
REVISION HISTORY
3/2023—Revision 0: Initial Version
User Guide DC3251A
PERFORMANCE SUMMARY
analog.com Rev. 0 | 4 of 13
Specifications are at TA = 25°C, unless otherwise noted.
Table 1. Performance Summary
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VOLTAGE RANGE
Input VIN 2.25 5.5 V
Output1VOUT 1.183 1.2 1.217 V
OUTPUT CURRENT IOUT 2 A
SWITCHING FREQUENCY fSW VIN > VOUT 1.6 2.0 2.4 MHz
TOP SWITCH MINIMUM ON-TIME tON 27 ns
TOP SWITCH DUTY CYCLE 100 %
1With 1% resistors. Accuracy improves to within 1% using 0.1% FB resistors or a fixed voltage version of the LTC3302A.
User Guide DC3251A
QUICK START PROCEDURE
analog.com Rev. 0 | 5 of 13
Demonstration circuit DC3251A is easy to set up and use to evalu-
ate the performance of the LTC3302A. For the proper measurement
equipment setup, see Figure 3 and follow the procedure below:
NOTE: For accurate VIN, VOUT, and efficiency measurements,
measure VIN at the VIN SNSE and GND SNSE turrets, and VOUT
at the VOUT SNSE and GND SNSE turrets as shown as VM1 and
VM2 in Figure 3. When measuring the input or output voltage ripple,
care must be taken to avoid a long ground lead on the oscilloscope
probe. Measure the output voltage ripple by touching the probe
tip directly across the output turrets or to TP1 as shown in Figure
4. TP1 is designed for a 50 Ω coax cable to reduce any high
frequency noise that might couple into the oscilloscope probes.
1. Set the JP1 Jumper to the SKIP position and JP2 to the HI
position.
2. With power off, connect the input power supply to VIN and GND.
If the input EMI filter is required, connect the input power supply
to VIN EMI.
3. Slowly increase PS1 to 1.0 V. If AM1 reads less than 20 mA,
increase PS1 to 3.3 V. Verify that VM1 reads 3.3 V and VM2
reads 1.2 V.
4. Connect an oscilloscope voltage probe as shown in Figure 4
in parallel with VM2. Set Channel to AC-coupled, voltage scale
to 20 mV and time base to 10 µs. Observe the VOUT ripple
voltage.
5. Verify that PGOOD turret is above 1 V.
6. Increasing the load by 1 A intervals up to 2 A and record VM1,
VM2, AM1, and AM2 for each interval.
7. Repeat step 6 for PS1 set to 2.5 V and again for PS1 set to 5.0
V.
8. Set the load to a constant 1 A. Remove the oscilloscope voltage
probe from VOUT. Place a ground clip on PGND terminal and
set the voltage scale to 1 V and the time scale to 500 ns/
Division. Trigger on the rising edge of the voltage probe. Using
a tip on the voltage probe, contact the SW node on the pad
of L1. Observe the duty cycle and the period of the switching
waveform (~500 ns).
9. Set the load current to 0.1 A and repeat step 8. Observe that
the switching waveform is now operating in pulse skip mode.
10. Move the jumper on JP2 to LO. Verify that VOUT reads 0 V
and verify that PGOOD is low. Return jumper on JP2 to HI and
verify that VM2 is 1.2 V and verify that PGOOD is above 1 V.
11. If forced continuous or Burst Mode is required, set PS1 to 0
V. Move JP1 to FC or BURST. Repeat steps 3 through 9. In
step 9, observe that the switching waveform is now operating in
forced continuous or Burst Mode.
12. To test the transient response with a base load, add the re-
quired resistor to produce a minimum load between VOUT and
RSNS turrets (RL shown on Figure 3). Note that the total load
resistance is RL plus R8 (100 mΩ).
13. Adjust a signal generator with a 10 ms period, 10% duty cycle,
and an amplitude from 1 V to 2 V to start.
14. Measure the RSNS voltage to observe the current, VRSNS/100
mΩ. Adjust the amplitude of the pulse to provide the required
transient. Adjust the rising and falling edge of the pulse to
provide the required ramp rate. For more details, see Figure 9
and the optional transient response circuit shown in Figure 6.
IOUT =VRSNS/100mΩ
(1)
15. When done, turn off PS1 and Load. Remove all connections to
the demo board.
User Guide DC3251A
EMI TEST RESULTS
analog.com Rev. 0 | 9 of 13
Figure 10. Conducted EMI Performance (CISPR25 Conducted Emission Test
with Class 5 Peak Limits)
Figure 11. Radiated EMI Performance (CISPR25 Radiated Emission Test with
Class 5 Peak Limits, Vertical)
Figure 12. Radiated EMI Performance (CISPR25 Radiated Emission Test with
Class 5 Peak Limits, Horizontal)
User Guide DC3251A
EVALUATION BOARD HARDWARE
analog.com Rev. 0 | 10 of 13
INTRODUCTION TO THE DC3251A
The DC3251A demonstration circuit features the LTC3302A, a
low voltage synchronous step-down regulator. The LTC3302A is
a monolithic, constant frequency, current mode step-down DC-DC
converter. A 2 MHz oscillator turns on the internal top power switch
at the beginning of each clock cycle. Current in the inductor then
increases until the top switch comparator trips and turns off the top
power switch. If the EN pin is low, the LTC3302A is in shutdown
and in a low quiescent current state. When the EN pin is above its
threshold, the switching regulator is enabled.
The MODE/SYNC pin sets the switching mode to pulse skip, forced
continuous, or Burst Mode. If an external 1.6 MHz to 2.4 MHz clock
is connected to the MODE/SYNC turret while the JP1 is set to
the SKIP position, the LTC3302A switching frequency sync to the
external clock. The LTC3302A operates in forced continuous mode
while syncing. For more detailed information, refer to the LTC3302A
data sheet.
ACCURATELY MEASURING OUTPUT RIPPLE
OF THE LTC3302A
With the fast edge rates of the circuit, high frequency noise can
be observed when measuring the output voltage with 1 MΩ termi-
nated oscilloscope probes. To better view the output ripple with
oscilloscopes of 400 MHz bandwidth and above a 50 Ω coax cable
connected as close to the output caps as possible should be used
with the oscilloscope channel terminated to 50 Ω at the scope.
This helps to reduce the noise coupling onto and displaying on the
scope. The demo board is set up to solder an U.FL, RECEPT, ST
SMD, 0 Hz to 6 GHz, 50 Ω connector (TP1) near the output cap
C6. These pads can also be used to solder a coax cable or other
oscilloscope probe connector if required.
The high frequency spikes are partially attributed to the inter-wind-
ing capacitance of the inductor and the voltage step is partially
attributed to the inductance in the output capacitors. This can
be reduced by choosing low ESL capacitors or adding small low
ESL capacitors in parallel to the output capacitors as close to the
inductor as possible. Figure 13 and Figure 14 show the output
ripple using a 500 MHz scope, 50 Ω probe with an added low ESL
X2Y capacitor added, C9, close to the inductor and GND return to
the input capacitors to reduce the inductance of the return path and
better filter the high frequency spikes.
Figure 13. VOUT Ripple Without C9 X2Y Capacitor
Figure 14. VOUT Ripple with C9 X2Y Capacitor
Indice
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