Cypress S6E1C1 Series Manuale del proprietario
S6E1C1/C3 Series
32-Bit Microcontroller
FM0+ Family
FLASH PROGRAMMING MANUAL
Publication Number S6E1Cx_MN710-00016-1v0-E Revision 1.0 Issue Date August 31, 2015
CONFIDENTIAL
For the information for microcontroller supports, see the following web site.
http://www.spansion.com/support/microcontrollers/
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Preface
Purpose of this manual and intended readers
This manual explains the functions, operations and serial programming of the flash memory of this series.
This manual is intended for engineers engaged in the actual development of products using this series.
Trademark
ARM and Cortex-M0+ are the trademarks of ARM Limited in the EU and other countries.
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
Organization of this Manual
This manual consists of the following 3 chapters.
CHAPTER 1 Flash Memory
This chapter gives an overview of, and explains the structure, operation, and registers of the Main
Flash memory.
CHAPTER 2 Flash Security
The flash security feature provides possibilities to protect the content of the flash memory.
This chapter section describes the overview and operations of the flash security.
CHAPTER 3 Serial Programming Connection
This chapter explains the basic configuration for serial write to flash memory by using the Fujitsu
Semiconductor Serial Programmer.
Sample programs and development environment
Cypress offers sample programs free of charge for operating the peripheral functions of the FM0+ family.
Cypress also makes available descriptions of the development environment required for this series. Feel
free to use them to verify the operational specifications and usage of this Fujitsu Semiconductor
microcontroller.
Microcontroller support information:
http://www.spansion.com/support/microcontrollers/
Note:
− Note that the sample programs are subject to change without notice. Since they are offered as a
way to demonstrate standard operations and usage, evaluate them sufficiently before running them
on your system.
Cypress assumes no responsibility for any damage that may occur as a result of using a sample
program.
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How to Use This Manual
Searching for a function
The following methods can be used to search for the explanation of a desired function in this manual:
Search from the table of the contents
The table of the contents lists the manual contents in the order of description.
Search from the register
The address where each register is located is not described in the text. To verify the address of a
register, see "APPENDIXES A. Register Map" of "FM0+ Peripheral Manual".
Terminology
This manual uses the following terminology.
Term
Explanation
Word
Indicates access in units of 32 bits.
Half word
Indicates access in units of 16 bits.
Byte
Indicates access in units of 8 bits.
Notations
The notations in bit configuration of the register explanation of this manual are written as follows.
− bit : bit number
− Field : bit field name
− Attribute : Attributes for read and write of each bit
− R : Read only
− W : Write only
− R/W : Readable/Writable
− - : Undefined
− Initial value : Initial value of the register after reset
− 0 : Initial value is "0"
− 1 : Initial value is "1"
− X : Initial value is undefined
The multiple bits are written as follows in this manual.
Example : bit7:0 indicates the bits from bit7 to bit0
The values such as for addresses are written as follows in this manual.
− Hexadecimal number : "0x" is attached in the beginning of a value as a prefix (example : 0xFFFF)
− Binary number : "0b" is attached in the beginning of a value as a prefix (example: 0b1111)
− Decimal number : Written using numbers only (example : 1000)
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Table 1 Applicable Products (FM0+ TYPE3-M0+ product list)
Type name*
Flash memory size
64Kbyte
128Kbyte
TYPE3-M0+
S6E1C11B0A
S6E1C11C0A
S6E1C11D0A
S6E1C31B0A
S6E1C31C0A
S6E1C31D0A
S6E1C12B0A
S6E1C12C0A
S6E1C12D0A
S6E1C32B0A
S6E1C32C0A
S6E1C32D0A
* : These type names are used to group applicable products in FM0+ Family peripheral manual.
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Table of Contents
CHAPTER1: Flash Memory........................................................................................................................... 7
1. Overview ........................................................................................................................................ 8
2. Configuration .................................................................................................................................. 9
3. Operations .................................................................................................................................... 13
3.1 Automatic Algorithm .......................................................................................................... 14
3.1.1 Command Sequences ...................................................................................... 15
3.1.2 Command Operations ...................................................................................... 16
3.1.3 Automatic Algorithm Run States ....................................................................... 18
3.2 Flash Memory Operation ................................................................................................... 20
3.2.1 Read/Reset Operation ...................................................................................... 21
3.2.2 Write Operation ................................................................................................ 22
3.2.3 Flash Erase Operation...................................................................................... 24
3.2.4 Sector Erase Operation .................................................................................... 25
3.2.5 Sector Erase Suspended Operation ................................................................. 27
3.2.6 Sector Erase Restart Operation ....................................................................... 28
3.3 Cautions When Using Flash Memory ................................................................................ 29
4. Registers ...................................................................................................................................... 30
4.1 Flash Read Wait Register (FRWTR) ................................................................................. 31
4.2 Flash Status Register (FSTR) ........................................................................................... 32
4.3 Flash Interrupt Control Register (FICR) ............................................................................. 34
4.4 Flash Interrupt Status Register (FISR) .............................................................................. 35
4.5 Flash Interrupt Clear Register (FICLR).............................................................................. 36
4.6 CR Trimming Data Mirror Register (CRTRMM) ................................................................. 37
4.7 Flash Sync Down Register (FSYNDN) .............................................................................. 38
CHAPTER2: Flash Security......................................................................................................................... 39
1. Overview ...................................................................................................................................... 40
2. Operation Explanation .................................................................................................................. 41
CHAPTER3: Serial Programming Connection........................................................................................... 43
1. Serial Programmer ............................................................................................................ 44
1.1. Basic Configuration ........................................................................................................... 45
1.2. Pins Used ......................................................................................................................... 53
Major Changes............................................................................................................................................. 55
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CHAPTER1: Flash Memory
This chapter explains the overview, configuration, operation,
and registers of the Flash memory.
This series is equipped with the Flash Memory of up to 128Kbyte for which Flash erase (simultaneous data
erase of all sectors), data erase of each sector, and data write with CPU can be implemented.
1. Overview
2. Configuration
3. Operations
4. Registers
CHAPTER1: Flash Memory
1.
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1. Overview
This series is equipped with up to 128Kbyte Flash Memory.
The built-in Flash Memory could erase data by-sector, or erase flash (erase data by-all-sector collectively),
and write programmed data by byte (8 bits) or by half-word (16 bits) with the Cortex-M0+ CPU.
Flash Memory Features
Usable capacity: Up to 128Kbyte (including 16Byte of security and trimming bytes)
Detection of write/erase completion with CPU interrupt
High-speed flash memory:
Up to 10 MHz: 0Wait
Operating mode:
1. CPU mode
This mode allows reading, writing, and erasing of flash memory from CPU (automatic algorithm*).
The operation of writing data by byte (8 bits) or by half word (16 bits) is available.
To rewrite data, execute a program on RAM.
2. ROM writer mode
This mode allows reading, writing, and erasing of flash memory from a ROM writer (automatic
algorithm*).
Built-in flash security function
(Prevents reading of the content of flash memory by a third party)
See "CHAPTER Flash Security" for details on the flash security function.
Note:
− This document explains the usage of flash memory in CPU mode.
For details on accessing the flash memory from a ROM writer, see the instruction manual of the
ROM writer that is being used.
*: Automatic algorithm = Embedded Algorithm
CHAPTER1: Flash Memory
2. Configuration
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2. Configuration
This series has maximum 128Kbyte of Flash memory area including a security code area, and a CR
trimming data area.
Table 2-1 shows the correspondence between Capacity of Flash Memory built into this series and Product
TYPE. Figure 2-1 to Figure 2-4 show the address and sector structure of the Main Flash memory built into
this series as well as the address of security/CR trimming data.
See "CHAPTER Flash Security" for details on the security.
See section "4.6 CR Trimming Data Mirror Register (CRTRMM)" and chapter "High-Speed CR Trimming" in
the "FM0+ Family Peripheral Manual" for details on the High-Speed CR trimming data.
Table 2-1 Flash Memory Capacity by FM0+ Product TYPE
Product TYPE
Flash Memory Capacity
64Kbyte
128Kbyte
TYPE3-M0+
S6E1C11B0A
S6E1C11C0A
S6E1C11D0A
S6E1C31B0A
S6E1C31C0A
S6E1C31D0A
S6E1C12B0A
S6E1C12C0A
S6E1C12D0A
S6E1C32B0A
S6E1C32C0A
S6E1C32D0A
CHAPTER1: Flash Memory
2. Configuration
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CONFIDENTIAL
Figure 2-1 Address and Sector Structure of 64Kbyte Flash Memory
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