Epson RTC-4573 Manuale utente

Page-1 Aug. 1998

Serial RTC with Alarm and Timer

RTC -4573

·Built-in frequency adjusted 32.768KHz crystal oscillator

·Serial interface that can be controlled through three signal lines

·Week , Day , hour , and minute alarm interrupt functions

·Interval timer interrupt function that can be set with an interval ranging from 1/4096th of a second to 255minutes

·Dual dedicated interrupt outputs for software maskable alarms and for timers

·Functions that detect halting of crystal oscillation, and when the time is being updated

·Automatic leap year compensation function

·Wide interface voltage range, from 1.6 to 5.5V

·Wide timing voltage range, from 1.6 to 5.5V

·Low current consumption : 0.5

A/3V (typ.)

·Small SOP package suited for high-density mounting

nOverview

This module is a serial interface-type real-time clock with a crystal oscillator on chip. This module includes clock

and calendar circuitry (from seconds to years) with automatic leap year compensation, alarms, and timer interrupt

functions, as well as functions that detect when oscillation is halted, the time is being updated. The serial

interface permits control through three signal lines, keeping the number of ports required on the system side to a

minimum. Because the small SOP package can be used in high-density mounting, this module is ideal for

portable telephones, hand-held terminals, and other compact electronic equipment.

nBlock Diagram

INTERRUPTS

CONTROLLER ALARM

OSC

/ TIRQ

BUS

INTERFACE

CIRCUIT SHIFT REGISTER

DATA

CLK

C E0

32.768KHz

CONTROL

DIVIDER CLOCK and

CALENDAR

CONTROL LINE

/ AIRQ

C E1

OUTPUT

CONTROLLER

FOUT TIMER

Page-2 Aug.1998

nPin Connection

8. GND

N.C

#9 #10

#18 17

11.

CLK

DATA

N.C

/ AIRQ

CE1

N.C

/ TIRQ

N.C

FOUT

CE0

Symbol Pin-No. I / O Function

CE1 5 Input

Chip enable 1 input pin.

This terminal has pull-down resistor built-in. Access to this RTC is possible in

"H" level both CE0,CE1 terminal. FOUT terminal can output frequency when

inputs "H" level into this terminal regardless of state of CE0 terminal. FOUT

terminal is high impedance state in input "L" level.

DATA 6 Bi-

directional

This I/O pin is used to for setting write mode/read mode, for writing an

address, and for reading and writing data. This pin functions either as an

input pin or an output pin, according to the write mode/read mode setting

made in the first 8 bits of input data following the rising edge of the CE input.

CLK 7 Input Shift clock input pin. In write mode, the data is read from the DATA pin at

the rising edge of the CLK signal; in read mode, the data is output from the

DATA pin at the rising edge of the CLK signal.

GND 9 - Connect to the negative (ground) line of the power supply.

/ TIRQ 10 Output Open drain interrupt output pin for the interval timer.

/ AIRQ 11 Output Output Open drain interrupt output pin for alarms.

CE0 12 Input

Chip enable 0 input pin.

When high, access to the internal registers is enabled. While low, the

DATA pin goes to high impedance. When the CE pin is set low, the fr, TEST,

and RESET bits are forcibly cleared to "0".Set this pin low when turning the

power on, when the device is not to be accessed, and when using the

backup power supply. This pin does not affect FOUT terminal.

FOUT 13 Output Frequency output terminal. Frequency is selectable by software.

VDD 14 - Connect to the positive line of the power supply.

Access is possible between 1.6 and 5.5V

N.C. 1,2,3,

4,8,

15,16,

17,18

Although these pins are not connected internally, they should always be left

open in order to obtain the most stable oscillation possible.

* Always connect a passthrough capacitor of at least 0.1

F as close as possible between VDD and GND.

Page-3 Aug.1998

nElectrical Characteristics

1. Absolute Maximum Ratings

Description Symbol Conditions Rated values Unit

Power supply Voltage VDD - -0.3 to +7.0 V

Input Voltage VIN1 input pins GND-0.3 to VDD+0.3 V

Output Voltage VOUT1 / TIRQ,/ AIRQ -0.3 to +8.0 V

VOUT2 FOUT,DATA GND-0.3 to VDD+0.3

Temperature TSTG - -55 to +125 °C

2. Operating Condition

Item Symbol Conditions MIN. MAX. Unit

Supply Voltage VDD -1.65.5V

Data Holding Voltage VCLK -1.65.5V

Operating Temperature Range TOPR °C

3. Frequency Characteristics

Item Symbol Conditions Specifications Unit

Frequency accuracy f / fo Ta=25 °C,VDD=3V 5 ±23 * ppm

Oscillator start up time tSTA Ta=25°C,VDD=1.6V 3 (MAX) sec

Temperature characteristics -10 to 70 °C 25 °C(Typ) +10 / -120 ppm

Voltage characteristics Ta=25°C,VDD=1.6 to 5.5V ±2.0 ppm / V

* Monthly error of about 1 minute

4. DC Characteristics (VDD =1.6 to 5.5V,Ta=-40 to 85°C )

Description Symbol Conditions MIN. TYP. MAX. Unit

Standby current 1 IDD1 VDD=5V CE0,CE1=GND - 1.0 2.0 mA

Standby current 2 IDD2 VDD=3V CE0,CE1=GND - 0.5 1.0 mA

Input Voltage VIH CE0,CE1 0.8VDD -V

DD V

VIL CLK,DATA pins 0 - 0.2VDD V

Input leakage current ILK VI=VDD or GND

CLK pins -0.5 - 0.5 mA

PulIdown R 1 RDWN1 VDD=5V 75 150 300 kW

PulIdown R 2 RDWN2 VDD=3V CE0,CE1 pins 150 300 600 kW

VOH1 VDD=5V IOH=-1mA 4.5 5.0 V

VOH2 VDD=3V DATA,FOUT pins 2.0 3.0 V

Output voltage 1 VOH3 VDD=3V IOH=-100mA

DATA,FOUT pins 2.9 3.0 V

VOL1 VDD=5V IOL=1mA GND+0.5 V

VOL2 VDD=3V DATA,FOUT pins GND+0.8 V

VOL3 VDD=3V IOL=100 mA

DATA,FOUT pins GND+0.1 V

Output voltage 2 VOL4 VDD=5V IOL=1mA GND+0.25 V

VOL5 VDD=3V / AIRQ,/ TIRQ pins GND+0.4 V

Leakage current IOZ VO=GND or VDD

DATA,/ AIRQ,/ TIRQ pins -0.5 0.5 mA

- +85

Page-4 Aug.1998

5. AC Characteristics ( CL=50pF,Ta=-40 to 85 )

VDD=3.0V±10% VDD=5.0V±10%

Description Symbol MIN. TYP. MAX. MIN. TYP. MAX. Unit

CLK clock cycle tCLK 1200 600 ns

CLK H Pulse Width tWH 600 - - 300 - - ns

CLK L Pulse Width tWL 600 - - 300 - - ns

CE setup time tCS 300 - - 150 - - ns

CE hold time tCH 400 - - 200 - - ns

CE recovery time tCR 600 - - 300 - - ns

CLK hold time tCKH 100 - - 50 - - ns

Write DATA in setup time tDS 50 - - 50 - - ns

Write DATA in hold time tDH 50 - - 50 - - ns

Read DATA in delay time tRD 0 - 400 0 - 200 ns

Output disable delay time tRZ - - 200 - - 100 ns

rise and fall time tRF - - 40 - - 20 ns

FOUT duty ratio

( 32.768kHz output ) Duty 35 - 65 40 - 60 %

CLK

C E

tWL

tWH

tCH

tCKH

50%

Write Mode ReadMode

CLK

DATA

CLK

DATA

C E

Hi-Z

tDH

tRF

C E

%50

%50 %90

%10

%90

%10

%50

°C

Page-5 Aug.1998

nRegister Table

Address Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0Secfos4020108421

1 Min fr 40 20 10 8 4 2 1

2 Hour fr * 20 10 8 4 2 1

3 Week fr 6 5 4 3 2 1 0

4Dayfr*20108421

5 Month fr * * 10 8 4 2 1

6 Year 80 40 20 10 8 4 2 1

7 Minutes Alarm AE 40 20 10 8 4 2 1

8 Hours Alarm AE * 20 10 8 4 2 1

9 Week Alarm AE 6 5 4 3 2 1 0

A Day Alarm AE * 20 10 8 4 2 1

B FOUT control FE * FD4 FD3 * FD2 FD1 FD0

C Timer interrupt control TE * TD1 TD0 * * * *

D Count Down Timer 128 64 32 16 8 4 2 1

E Control 1 * * * TI/TP AF TF AIE TIE

F Control 2 * TEST STOP RESET HOLD * * *

1.1 Timekeeping/calendar registers (register 0 to register 6)

·The data in these registers is BCD format. For example, "0101 1001" represents 59 seconds. In addition, the

"*" mark in the register table means that the register is readable and writable, and can be used as RAM. Time is

kept in the 24-hour format.

·Writing to a bit marked with an asterisk ("*") is permitted; such bits can be used as RAM. When the alarm and

timer functions are not used, registers 7 to A can be used as 8-bit memory registers, and registers C and D can

be used as 7-bit memory registers.

·Year register and leap years

A leap year is detected by dividing the two BCD digits of the year register by four; if the remainder is zero, the

year is a leap year. Therefore, leap years can be automatically determined whether the year is numbered

according to the western calendar or the Japanese calendar (year of Heisei).

·Day of the week

The day of the week register uses 7 bits, from 0 to 6; the meanings of the bits are shown in the table below. Do

not set more than one bit to "1" at any one time.

bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 day of week

0000001Sunday

0000010Monday

0000100Tuesday

0001000

Wednesday

0010000Thursday

0100000 Friday

1000000Saturday

·fos ( OSC Flag )

This flag uses it for a monitor of battery listing degradation with the binary digit which that oscillation stopped is

set at. Oscillation stopping shows "1", and it is cleared by writing in "0". But fo flag can't write in "0" when

oscillation stopped. And fo can write in "1", but don't write in it. Other binary digit (HOLD,STOP,RESET) doesn't

receive affect even in case of "1".

·fr ( READ Flag )

It is the binary digit that turn into "1" when CE was input, and carry occurred during "H" for 1 second. The distinction

that carry to a figure rose during (CE input ="H" during readout of register in an indicator by this for 1 second is

possible. When fr was "1", I need to read register in all indicators once again.

1.2 Alarm registers (register 7 to register A)

Alarms can be set for days of the week, hours, and minutes. Bit 7 of each alarm register is an AE bit that can be

used to set an hourly alarm or a daily alarm. An alarm can also be set for multiple days of the week.However, when

using the day of the week alarm, also set either or both the hour and minute alarms. If the day of the week alarm is

set by itself, the alarm may not be output properly.When the AE bit is "0", the register in question and the timekeeping

regardless of the data.

1.3. Frequency output control register ( Reg-B )

FE bit is Frequency output enable bit. Source clock is selectable by FD4 and FD3 bits. And Count down rate is

selectable by FD0 , FD1 and FD2 bits. This frequency is output from FOUT terminal.

FOUT control ( Reg.B ) FD2  FD1  FD0  Div.  FOUT Duty

 0  0  0  1 / 1  50%

 0  0  1  1 / 2  50%

 0  1  0  1 / 3  33%

 0  1  1  1 / 6  50%

 1  0  0 1 / 5  20%

 1  0  1  1 / 10 50%

 1  1  0  1 / 15 33%

 1  1  1  1 / 30 50%

FD4  FD3  Source Clk.

0  0  32768Hz

0  1  1024Hz

1  0  32Hz

1  1  1Hz

1.4. Timer register( Reg-C to Reg-D )

Source clock of this counter does setup by TD bit of Register-C.

When data of register-D becomes 0, /TIRQ terminal changes to Low level.

In that time, register-D does written data reloads again if TI/TP bit is 1.

And counter does countdown repeatedly.

As a result, by a same period, interrupt occurs repeatedly.

When TIE bit of Register-E is "0", /TIRQ terminal keep high impedance.

When TI/TP bit is 0, Register-D does never reload the data.

Set TI/TP.TD,TIE and TE bits carefully, for perfect function of timer.

Source clock control for Timer ( Reg.C )

TD1  TD0  Source Clk.

 0  0  4096Hz

 0  1  64Hz

 1  0 sec.  update

 1  1 min.  update

Page-6 Aug.1998

When TEbit is 0, Register-D loads preset data, and keeps stop. Note:There isn't pause.

When TE bit is cleared, Register-D starts countdown from preset data.

Timer interrupt doesn't occur when set 0 in Register-D.

Therefore pay attention because 1 period error of source clock occurs as for timer time.

Timing of Timer start

DATA

TIRQ-PIN

TIMER COUNT DOWN

COUNT DOWN

CLK

DATA LOAD

ZERO

TD0 TD1 *TE

Address C

Page-7 Aug.1998

1.5. Control register1 ( Reg-E )

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

E * * * TI/TP AF TF AIE TIE

TI / TPbits: ( Interrupt Signal Output Mode Select. Timer-Interrupt / Timer-Periodic )

output mode of timer signaling.

bit 0 1

TI / TP

TIRQ terminal is maintained by "L" till it is

written in "0" at TF bit when turn into interrupt

mode, and timer interrupt occurs, and, but,

timer interrupt signal does it with TIE=1

Timer interrupt signaling is set in a mode

repeatedly. When timer interrupt occurs,

TIRQ terminal is set at "L" immediately and,

but, does it with TIE=1. TF bit is set in "1",

and TIRQ terminal is set in Hi-Z after

approximately 3.9 m s, and TF bit holds "1" till

it is write clear by "0".

AF / TF bits: ( Alarm Flag / Timer Flag )

When alarm occurs, AF bit is set in "1", and a timer is set in "1" at 0 o?clock, and TF bit can?t write in "1" at both bit.

AIE,TIE bits: ( Alarm / Timer Interrupt Enable )

It is decided whether IRQ terminal drives it when alarm, timer interrupt occurred, and AIE corresponds in alarm, and

TIE corresponds to a timer, and AIRQ terminal is set in case of "0" AIE bit by Hi-Z, and TIRQ terminal is set in case of

"0" TIE bit by Hi-Z.

1.6 Control register 2 (register F )

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

F * TEST STOP RESET HOLD * * *

·TEST bit : This is a test bit for Seiko-Epson?s use.

Always set this bit to "0". When writing to the other bits in the CF register, be careful not to accidentally write a "1" to

this bit. This bit is cleared by setting CE low.

·STOP bit

If this bit is set to "1", timekeeping stops (after 4KHz). If this bit is set back to "0", timekeeping resumes.

·RESET bit

Setting this bit to "1" resets the counter below the seconds counter, stopping timekeeping. If a "1" is written to this bit,

it is cleared either by writing a "0" to this bit again with the auto increment function, or by setting CE low.

The only effect on timekeeping precision is a maximum error 61 [micro]s. This bit is unaffected by the status of other

bits.

·HOLD bit

This bit stops carries to the ones digit of the seconds counter. Timekeeping continues below the seconds counter,

and if there was a carry to the seconds counter while HOLD = 1, compensation (by means of adding one second) is

made immediately (within 0 to 122 [micro]s) after HOLD is released.This bit is cleared by writing a "0" to it.

Page-8 Aug.1998

nUsage

Functional Overview

The basic sequence for reads and writes is the same: after the CE input goes high, the 4-bit mode is set, the 4-bit

address is specified, and then the data is read or written in 8-bit units.If the input of an 8-bit unit of data is not yet

complete when the CE input is set low, the 8-bit data that was being written when the CE input went low is ignored.

(Prior data is valid. Also, in these circumstances, the WF bit is set to "1", indicating that the write operation was not

completed normally.)Writes and reads are both LSB first.

[ Writes ]

1) After the CE input goes high, set the value of the first four write bits is to "3", indicating write mode, and then set

the address to be written in the next four bits.

2) The 8 bits of write data that follow are written to the address that was set; the address is then automatically

incremented, and the next 8 bits of data are written to the new address.

3) The automatic address incrementation is cyclic, with address 0 following address F.

D0 D1 D2 D3 D0 D1 D4 D5D2 D3 D2 D3 D6 D7

C E

CLK

DATA D0 D1 D0 D1 D4 D5D2 D3 D6 D7

[ Reads ]

1) After the CE input goes high, set the value of the first four write bits to "C", indicating read mode, and then set the

address to be written in the next four bits.

2) The 8 bits of data that follow are read from the address that was set; the address is then automatically

incremented, and the next 8 bits of data are read from the new address.

3) The automatic address incrementation is cyclic, with address 0 following address F.

D0 D1 D2 D3 D0 D2

C E

CLK

DATA D0 D2 D4 D6 D0 D2 D4 D6

If the mode setting code was set to a value other than "C" or "3", the subsequent data is ignored and the DATA pin

remains in the input state.

- - -

Write mode

CODE=3 (0011) Write to address (N) Write DATA to (N) Write DATA

(to address N + 1)

Set readout mode

CODE=C (1100) READ address (N) READ DATA

(address N) READ DATA

( address N + 1)

- - -

- - - -

Page-9 Aug.1998

nExamples of External Connections

RTC4573

VDD

CE1

GND

Voltage

Detector

4.7uF

0.1uF

Schottky

Barrier

Diode

Note

VDD D 1

D 1 : 1SS108 or Equivalent Vf = 0.1V

VDD

VSS

SCI7701

or SCI7721

CE0

DATA

CLK

/ TIRQ

/ AIRQ

FOUT

nPackage Outline

7.8 0.2

5.4

11.4 0.2

1.270.4

1.8 2.0

0.12 0.1

MAX.

0.15

0.6

0 - 10 0.2

MIN.

Page-10 Aug.1998

nReference data

( 1 ) Frequency temperature characteristics

( typical )

qT= 25°C TYP.

a= -0.035ppm/°C² TYP.

Temperature [°C]

Frequency dft[ppm]

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

-40-30-20-100 1020304050607080

Finding the frequency stability (clock error)

1. The frequency temperature characteristics can be

approximated by using the following expression:

DfT(ppm)=a(qT-qX)2

DfT(ppm) : Frequency deviation at target temperature

a(ppm/ 2: Secondary temperature coefficient

(-0.035 0.005ppm/ 2)

() : Peak temperature

: Target temperature (25 5 )

2. To determine the overall clock accuracy, add the

frequency tolerance and the voltage characteristics:

Df/f(ppm) = Df/f0 + DfT+ DfV

Df (ppm) : Clock accuracy at a given temperature

and voltage

: Frequency tolerance

: Temperature dependent frequency

deviation

: Voltage dependent frequency deviation

Df (ppm)/f0

(ppm)

3. Finding the daily deviation:

Daily deviation (seconds) = Df/f x 10-6 x 86400

The clock error is one second per day at 11.574 ppm.

( 2 ) Frequency voltage characteristics

( typical )

- 5

Frequency[ppm]

Supply voltage VDD[V]

- 10

+ 10

+ 5

345

Conditions

3V reference , Ta=+25°C

( 3 ) Current consumption voltage characteristics

( typical )

Current consumption [µA]

Supply voltage VDD[V]

345

Conditions

CE0,CE1=0V,No load

Ta=+25

Note : This data shows average values for a sample lot.

For rated values, see the spacifications on page 3.

)

°C

°C°C

()

°C±

°C

Indice

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