Infineon XMC4500 series Manuale utente

Reference Manual

V1.6 2016-07

Microcontrollers

XMC4500

Microcontroller Series

for Industrial Applications

XMC4000 Family

ARM®Cortex®-M4

32-bit processor core

Edition 2016-07

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approvalofInfineonTechnologies, if afailureofsuchcomponentscanreasonablybe expectedtocause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Reference Manual

V1.6 2016-07

Microcontrollers

XMC4500

Microcontroller Series

for Industrial Applications

XMC4000 Family

ARM®Cortex®-M4

32-bit processor core

XMC4500

XMC4000 Family

Reference Manual V1.6, 2016-07

XMC4500 Reference Manual

Revision History: V1.6 2016-07

Previous Versions:

V1.5, 2014-07

Page Subjects

2-83,

2-108ff.

Updated CPU chapter

• Corrected register AFSR and MVFRx to match register definition

used by compilers and other development tools.

multiple,

4-23ff.,

4-35ff.

Updated Service Request Processing chapter

• Corrected SCU register name RAWSR to SRRAW.

• “Service Request Generation” section revised.

• ERU0 outputs not connected directly to NVIC but routed thru SCU.

Corrected in ERU0 tables.

multiple,

13-78ff.

Updated SDMMC chapter

• Removed SPI register and sections describing SPI mode support.

• Added CAPABILITIES register.

multiple,

15-80,

15-83,

none,

15-283,

15-286,

15-289,

15-291,

15-292,

15-293,

15-295,

15-296,

15-299,

15-332

Updated ETH chapter

• Consistency with SCU naming (for example fSYS) improved.

• Improved figure on SMA Interface Block.

• Improved section on RMII.

• Removed register PPS_CONTROL, feature is not used.

• Register description improved for

– TIMESTAMP_CONTROL

– SUB_SECOND_INCREMENT

– SYSTEM_TIME_NANOSECONDS_UPDATE

– TIMESTAMP_ADDEND

– TARGET_TIME_SECONDS

– TARGET_TIME_NANOSECONDS

– SYSTEM_TIME_HIGHER_WORD_SECONDS

– TIMESTAMP_STATUS

–BUS_MODE

• Revised “Interconnects” section

26-1 Adjusted text style only to match Infineon standard.

Previous Versions:

V1.4, 2014-04

Page Subjects

Subject to Agreement on the Use of Product Information

XMC4500

XMC4000 Family

Reference Manual 1-2 V1.6, 2016-07

13-43 Updated SDMMC chapter

• Added bit declaration and description of bit

SDMMC_HOST_CTRL.SD_8BIT_MODE.

19-1ff. Updated ADC chapter

• Previous version described some non existing register bits

regarding boundary flags

Previous Versions:

V1.3, 2013-08

Page Subjects

2-102,

2-108f.

Updated CPU chapter

• Corrected FPCCR reset value

• Added MVFR0 and MVFR1 register descriptions

5-24 Corrected figure “Channel FIFO contents” in GPDMA chapter.

11-1ff. SCU chapter enhanced for readability.

12-13,

12-23,

12-26,

12-31

Updated LEDTS chapter

• Added typical fequency range in section on Finger Sensing

• Module ID.MOD_REV starts with 00H

• Clarified limitation on bit field FNCTL.NR_LEDCOL for value 111B

• Corrected TSVAL.TSCTRVALR bit field type to “rh”

14-16f.,

14-23.

Updated EBU chapter

• Improved External Memory Regions section

• Replaced alignment description by a table

15-332 Removed multiplexed outputs from interconnects table and added two

footnotes.

17-163,

17-227ff.

Updated USIC chapter

• CCFG register reset value corrected

• Added hints on the signal usage to Interconnect tables

26-1 “Startup Modes” chapter enhanced for readability.

27-12 Added Infineon JTAG ID code information to table in DEBUG chapter.

Previous Versions:

V1.2, 2012-12

V1.1, 2012-07

V1.0, 2012-02

Page Subjects

XMC4500 Reference Manual

Revision History: V1.6 2016-07

Subject to Agreement on the Use of Product Information

XMC4500

XMC4000 Family

Reference Manual 1-3 V1.6, 2016-07

Trademarks

C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.

ARM®, ARM Powered®and AMBA®are registered trademarks of ARM, Limited.

Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™, Embedded Trace

Buffer™ and Thumb®are trademarks of ARM, Limited.

Replaced occurences of fPB by fPERIPH in several locations.

11-157,

11-10ff.

SCU chapter

• Width of OSCHPCTRL.OSVAL bit field changed from 5 to 4 bits.

• Described DTS calibration mechanism.

12-36ff. Added PORT connections to Interconnects section in LEDTS chapter.

14-1ff. EBU chapter

• Reworked Introduction and SDRAM sections for improved

readability.

• Corrected address bus width 25 -> 24 lines.

• Restructured the registers section to reflect functional groups.

15-1ff. Improved figures and register overview table in ETH chapter.

17-1ff. USIC chapter

• Abbreviations table is added

• When in slave mode and SCLKCFG=01B, bit DX1CR.DPOL needs

to be set to 1, see Section 17.4.1.2

• Description on SCLKCFG setting is removed from Section 17.6.3

• Assignment of USICx_SRy to GPDMA is updated.

• Coding for WLENx bit field in RBUF01SR register is updated to

consider dual and quad SSC modes.

21-1ff. DAC chapter

• NEGATE function added for later design steps (not in AA, AB, AC)

• Behavior after setting ANAEN bit (tSTARTUP time) clarified

25-30ff.,

25-38ff. PORTS chapter

• Added Ethernet MII input connections shared with RMII

connections.

• Corrected EBU.BC[2:3] to active low signals (BCx#).

• Renamed EBU.RD/EBU.WR# to EBU.RD_WR#.

• Added note on driver mode on hardwired pins (HIB_IOs and TMS).

27-12 Revised the ROM table section in DEBUG chapter.

XMC4500 Reference Manual

Revision History: V1.6 2016-07

Subject to Agreement on the Use of Product Information

XMC4500

XMC4000 Family

Reference Manual 1-4 V1.6, 2016-07

Synopsys™ is a trademark of Synopsys, Inc.

We Listen to Your Comments

Is there any information in this document that you feel is wrong, unclear or missing?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.commen[email protected]

Subject to Agreement on the Use of Product Information

Reference Manual L-1 V1.6, 2016-07

XMC4500

XMC4000 Family

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 CPU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3 On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4 Communication Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.5 Analog Frontend Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.6 Industrial Control Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.7 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.1 Processor Mode and Privilege Levels for Software Execution . . . . . . 2-4

2.2.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.3 Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.2.4 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.2.5 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.2.6 The Cortex Microcontroller Software Interface Standard . . . . . . . . . . 2-17

2.2.7 CMSIS functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.3 Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.1 Memory Regions, Types and Attributes . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.3.2 Memory System Ordering of Memory Accesses . . . . . . . . . . . . . . . . 2-21

2.3.3 Behavior of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.3.4 Software Ordering of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . 2-23

2.3.5 Memory Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.6 Synchronization Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.3.7 Programming Hints for the Synchronization Primitives . . . . . . . . . . . 2-26

2.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.5 Exception Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.5.1 Exception States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.5.2 Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.5.3 Exception Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29

2.5.4 Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

2.5.5 Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.5.6 Interrupt Priority Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

2.5.7 Exception Entry and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.6 Fault Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

2.6.1 Fault Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Table of Contents

Subject to Agreement on the Use of Product Information

XMC4500

XMC4000 Family

Table of Contents

Reference Manual L-2 V1.6, 2016-07

2.6.2 Fault Escalation and Hard Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.6.3 Fault Status Registers and Fault Address Registers . . . . . . . . . . . . . 2-39

2.6.4 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

2.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.7.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

2.7.2 Wakeup from Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.7.3 The External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41

2.7.4 Power Management Programming Hints . . . . . . . . . . . . . . . . . . . . . . 2-42

2.8 Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.8.1 About the Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.8.2 System control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

2.8.2.1 System control block design hints and tips . . . . . . . . . . . . . . . . . . 2-43

2.8.3 System timer, SysTick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.8.3.1 SysTick design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

2.8.4 Nested Vectored Interrupt Controller (NVIC) . . . . . . . . . . . . . . . . . . . 2-43

2.8.4.1 Level-sensitive and pulse interrupts . . . . . . . . . . . . . . . . . . . . . . . 2-44

2.8.4.2 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

2.8.4.3 Using CMSIS functions to access NVIC . . . . . . . . . . . . . . . . . . . . 2-45

2.8.5 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.8.5.1 MPU Access Permission Attributes . . . . . . . . . . . . . . . . . . . . . . . . 2-48

2.8.5.2 MPU Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.8.5.3 Updating an MPU Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

2.8.5.4 MPU Design Hints and Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.8.6 Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.8.6.1 Enabling the FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.9 PPB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.9.1 SCS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58

2.9.2 SysTick Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

2.9.3 NVIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

2.9.4 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93

2.9.5 FPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-101

3BusSystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Bus Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

4 Service Request Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Service Request Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Interrupt Service Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.4 DMA Line Router (DLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Subject to Agreement on the Use of Product Information

XMC4500

XMC4000 Family

Table of Contents

Reference Manual L-3 V1.6, 2016-07

4.4.2 DMA Service Request Source Selection . . . . . . . . . . . . . . . . . . . . . . 4-10

4.5 Event Request Unit (ERU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.5.1 Event Request Select Unit (ERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

4.5.2 Event Trigger Logic (ETLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

4.5.3 Cross Connect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

4.5.4 Output Gating Unit (OGUy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

4.6 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

4.7 Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

4.8 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

4.9 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . 4-23

4.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

4.10.1 DLR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

4.10.2 ERU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

4.11 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

4.11.1 ERU0 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.11.2 ERU1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

5 General Purpose DMA (GPDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.2 Variable Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.2.3 Flow Controller and Transfer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.2.4 Handshaking Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.2.4.1 Hardware Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.2.4.2 Software Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.2.4.3 Handshaking with GPDMA as Flow Controller . . . . . . . . . . . . . . . 5-11

5.2.4.4 Handshaking with Peripheral as Flow Controller . . . . . . . . . . . . . . 5-13

5.2.5 FIFO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

5.2.6 Bus and Channel Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.2.7 Scatter/Gather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.2.8 Abnormal Transfer Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.3 Basic Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

5.3.1 Block transfer with GPDMA as the flow controller . . . . . . . . . . . . . . . 5-22

5.3.2 Effect of maximum AMBA burst length on a block transfer . . . . . . . . 5-23

5.4 Multi Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

5.4.1 Block Chaining Using Linked Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

5.4.2 Auto-Reloading of Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . 5-32

5.4.3 Contiguous Address Between Blocks . . . . . . . . . . . . . . . . . . . . . . . . 5-32

5.4.4 Suspension of Transfers Between Blocks . . . . . . . . . . . . . . . . . . . . . 5-32

5.4.5 Ending Multi-Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33

Subject to Agreement on the Use of Product Information

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