Linear Technology Analog Devices DC2688A Guida rapida alla configurazione

DEMO MANUAL DC2688A

Rev. 0

DESCRIPTION

LT8698S/LT8698S-1

5V 3A, 42V Input USB Charger with Cable Drop

Compensation and Data Line Protection

Demonstration circuit 2688A is a USB charger designed

to power the 5V USB V

BUS

rail with up to 3A from an

input voltage as high as 42V. The DC2688A circuit fea-

tures the LT

8698S/LT8698S-1, which is a compact, high

efficiency, high speed synchronous monolithic step-down

switching regulator which features the second-genera-

tion Silent Switcher

technology that minimizes EMI and

reduces PCB layout sensitivity. The LT8698S/LT8698S-1

supports a wide variety of portable device charger pro-

files including USB BC 1.2 CDP, DCP, and SDP as well as

common proprietary charger profiles, all of which can

be easily evaluated using the DC2688A demo board. The

LT8698S/LT8698S-1 also features high speed USB 2.0

compliant data line switches, robust data line protection,

and programmable cable drop compensation which main-

tains accurate 5V VBUS regulation even when USB sockets

are separated from the LT8698S/LT8698S-1 by a long

cable. These features make the LT8698S/LT8698S-1 well

suited for automotive USB host applications.

There are two assembly versions. The DC2688A-A fea-

tures the LT8698S, while the DC2688A-B features the

LT8698S-1. The difference is that the LT8698S includes

VIN hot loop capacitors inside the IC package for improved

EMI/EMC performance, while the LT8698S-1 does not

include these capacitors.

DEMO BOARD INFORMATION

The main power stage of the DC2688A demo board oper-

ates at 2MHz switching frequency by default to minimize

solution size. The jumper JP5 on the demo board deter-

mines the configuration of the SYNC pin of the LT8698S/

LT8698S-1. Setting the jumper JP5 to “FCM W/SSM”

location ties SYNC pin to INTV

which enables forced

continuous mode with spread-spectrum modulation for

improved EMI performance. Moving JP5 to “PSK” loca-

tion enables the pulse-skipping mode which improves

light load efficiency by reducing the switching frequency

All registered trademarks and trademarks are the property of their respective owners.

at light load and reducing VIN quiescent current between

pulses. To synchronize to an external clock, move JP5

to “FCM W/O SSM or SYNC”location and apply external

clock on the EXT_SYNC turret.

Figure1 shows a functional Block Diagram of the DC2688A

demo board.

The DC2688A demo board includes a re-timer IC USB2422

whose purpose is to ensure that USB high speed signaling

eye pattern can be measured at test plane2 as defined by

USB 2.0 specifications, and that such signaling through

the LT8698S/LT8698S-1’s USB data line switches con-

forms to template 1 eye pattern requirements. Please note

that a re-timer IC is not necessary in actual applications

as the USB host controller will reside on the same PCB

board as the LT8698S/LT8698S-1.

The DC2688A demo board includes three headers JP2,

JP3, and JP4, which are used for manual control of the

LT8698S/LT8698S-1’s tristate input pins SEL1, SEL2, and

SEL3. Although these select pins are intended to interface

with a USB host microcontroller, majority of the functions

of the LT8698S/LT8698S-1 may be evaluated by simply

using the manual selection of the SEL1, SEL2, and SEL3

headers on the DC2688A board.

The DC2688A demo board is 3.5-inch × 3.5-inch in size

and has four copper layers with 2oz copper on the outer

layers and 1oz copper on the inner layers. The DC2688A

has controlled impedance transmission lines placed for

high speed differential USB data signaling, in between the

USB-B receptacle, the USB2422 re-timer IC, the LT8698S/

LT8698S-1 data line switches, and the USB-A receptacle,

with a differential characteristic impedance of 90Ω.

The default rated maximum load current of the DC2688A

is 2.4A, with a default RSENSE resistor value of 10mΩ.

However, the DC2688A circuit can supply 3A load current

with a RSENSE resistor value of 8mΩ.

Design files for this circuit board are available.

DEMO MANUAL DC2688A

Rev. 0

DESCRIPTION

Figure2 shows the efficiency of the DC2688A at 12V and

24V input in pulse-skipping mode of operation (input from

VIN turret pin, and RSENSE resistor is 8mΩ)

The DC2688A has an input EMI filter installed. The EMI

performance of the demo board DC2688A-A (with EMI

filter) is shown in Figure3 and Figure4. The red lines in

Figure3 are CISPR 25 class 5 limits for peak detector. The

EMI performance of DC2688A-B (with EMI filter) is shown

in Figure5 and Figure6. To achieve EMI performance as

shown in Figure3 through Figure6, the input EMI filter

is required, and the input voltage should be applied at

VEMI terminal.

As shown in the dashed box in Figure1 functional block

diagram, the DC2688A demo board may also be optionally

used in conjunction with the Linduino

microcontroller

board DC2026Cand a touchscreen display shield. The

DC2688A demo board includes the AD5593R, which is

an 8-channel ADC/GPIO with on-chip reference and I2C

interface. The AD5593R monitors several inputs from the

LT8698S/LT8698S-1, communicates with the Linduino

board through the I2C interface, and controls the SEL1,

SEL2, and SEL3 tristate input pins.

The LT8698S/LT8698S-1 data sheet gives a complete

description of the part, operation and application infor-

mation. The data sheet must be read in conjunction with

this manual forDC2688A.

DEMO MANUAL DC2688A

Rev. 0

Figure1. DC2688A Demo Board Functional Block Diagram

DESCRIPTION

DEMO MANUAL DC2688A

Rev. 0

Figure2. Efficiency vs Load Current at 2MHz Switching Frequency (Input from VIN Terminal)

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 24V

VIN = 12V

IOUT (A)

0.5

1.5

2.5

EFFICIENCY (%)

DC2688A F02

fSW = 2MHz

PULSE SKIPPING MODE

L = XFL5030-222

RSENSE = 8mΩ

PERFORMANCE SUMMARY

Specifications are at TA= 25°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input Supply Range 6.0 42 V

VBUS USB 5V Bus Voltage Without Cable Drop Compensation 4.8 5 5.2 V

USB 5V Bus Voltage With Cable Drop Compensation 6.2 V

IBUS Maximum Output Current RSENSE = 10mΩ 2.4 A

Maximum Output Current RSENSE = 8mΩ 3.0 A

fSW Switching Frequency 1.95 2 2.05 MHz

EFE Efficiency at DC VIN = 12V, IBUS1 = 1.5A 92.7 %

DEMO MANUAL DC2688A

Rev. 0

Figure3. DC2688A-A Demo Circuit EMI Performance in CISPR 25

Radiated Emissions Test, Peak Detector

Figure4. DC2688A-A Demo Circuit EMI Performance in CISPR 25

Radiated Emissions Test, Average Detector

DC2688A–A DEMO BOARD

(WITH EMI FILTER INSTALLED)

14V INPUT TO 5V

BUS

OUTPUT AT 2.5A, f

= 2MHz

L1 = XFL4020–222ME, C

VIN2

AND C

VIN3

POPULATED

VERTICAL POLARIZATION

PEAK DETECTOR

CLASS 5 PEAK LIMIT

SPREAD SPECTRUM MODE

FIXED FREQUENCY MODE

FREQUENCY (MHz)

100

200

300

400

500

600

700

800

900

1000

AMPLITUDE (dBµV/m)

DC2688A F03

DC2688A–A DEMO BOARD

(WITH EMI FILTER INSTALLED)

14V INPUT TO 5V

BUS

OUTPUT AT 2.5A, f

= 2MHz

L1 = XFL4020–222ME, C

VIN2

AND C

VIN3

POPULATED

VERTICAL POLARIZATION

AVERAGE DETECTOR

CLASS 5 AVERAGE LIMIT

SPREAD SPECTRUM MODE

FIXED FREQUENCY MODE

FREQUENCY (MHz)

100

200

300

400

500

600

700

800

900

1000

–10

–5

AMPLITUDE (dBµV/m)

DC2688A F04

TYPICAL PERFORMANCE CHARACTERISTICS

Figure5. DC2688A-B Demo Circuit EMI Performance in CISPR 25

Radiated Emissions Test, Vertical Polarization

Figure6. DC2688A-B Demo Circuit EMI Performance in CISPR 25

Radiated Emissions Test, Horizontal Polarization

CLASS 5 PEAK LIMIT

SPREAD SPECTRUM MODE

FIXED FREQUENCY MODE

VERTICAL POLARIZATION

PEAK DETECTOR

FREQUENCY (MHz)

100

200

300

400

500

600

700

800

900

1000

AMPLITUDE (dBµV/m)

DC2688A F05

DC2688A-B DEMO BOARD (WITH EMI FILTER INSTALLED)

14V INPUT TO 5V VBUS AT 2.5A, fSW = 2MHz, L1 = XFL4020-222ME,

CVIN2 AND CVIN3 POPULATED

CLASS 5 PEAK LIMIT

SPREAD SPECTRUM MODE

FIXED FREQUENCY MODE

HORIZONTAL POLARIZATION

PEAK DETECTOR

FREQUENCY (MHz)

100

200

300

400

500

600

700

800

900

1000

AMPLITUDE (dBµV/m)

DC2688A F06

DC2688A-B DEMO BOARD (WITH EMI FILTER INSTALLED)

14V INPUT TO 5V VBUS AT 2.5A, fSW = 2MHz, L1 = XFL4020-222ME,

CVIN2 AND CVIN3 POPULATED

DEMO MANUAL DC2688A

Rev. 0

EVALUATE DC2688A POWER STAGE

Demonstration circuit 2688A is easy to set up to evalu-

ate the performance of the LT8698S/LT8698S-1. Refer to

Figure7 for proper measurement equipment setup and

follow the procedure below.

NOTE: When measuring the input or output voltage

ripple, care must be taken to avoid long ground lead

on the oscilloscope probe. Measure the output voltage

ripple by touching the probe tip directly across the

VBUS and GND terminals. See Figure7 and Figure8

for proper measurement technique.

1. Check that JP6 and JP7 are placed on the OFF position

to ensure that the on-board LDOs are disabled.

2. Place JP2, JP3, and JP4 all on the “Z” position, which

puts the LT8698S/LT8698S-1 in VBUS only mode of

operation with VBUS in regulation.

3. With power off, connect the input power supply to

VEMI and GND turrets. If the EMI/EMC performance

is not important, connect the input power supply to

VIN and GND turrets.

4. With power off, connect the loads from VBUS to GND.

5. Check that JP1 EN jumper is placed on the ONposition.

6. Turn on the power at the input.

NOTE:Make sure that the input voltage never

exceeds42V.

7. Check for proper output voltages:VBUS voltage should

be between 5V to 6.1V and depends on the cable drop

QUICK START PROCEDURE

compensation settings, and D11 LED indicator lights

up in green. For more information on cable drop

compensation, please refer to LT8698S/LT8698S-1

datasheet.

NOTE: If there is no output, temporarily disconnect

the load to make sure that the load is not set too high.

8. Once the proper output voltages are established,

adjust the load within the operating ranges and

observe the output voltage regulation, ripple voltage,

efficiency and other parameters.

9. An external clock can be added to the EXT_SYNC ter-

minal when SYNC function is used (JP5 on the FCM

W/O SSM OR SYNC position). Please make sure that

R37 resistor should be chosen to set the LT8698S/

LT8698S-1 switching frequency equal to or below the

lowest synchronization frequency. JP5 can also set

the LT8698S/LT8698S-1 in spread-spectrum mode

(JP5 on the FCM W/SSM position) or pulse skipping

mode (JP5 on the PSK position).

10. Check STATUS pin voltage on the STATUS turret in

relation to the IBUS load current. If IBUS load is lower

than 100mA typically, STATUS pin should be low, and

the STATUS LED lights up in yellow;if IBUS load is

higher than 130mA typically, STATUS pin should be

high, and the STATUS LED does not light up.

11. Check IMON point voltage, in relation to IBUS load cur-

rent. Measure the voltage on the IMON turret:the

IMON voltage should be equal to 0.46V/A in propor-

tion to the IBUS load current.

DEMO MANUAL DC2688A

Rev. 0

Figure7. Proper Measurement Equipment Setup for Evaluating the DC2688A-B Power Stage

QUICK START PROCEDURE

Figure8. Measuring Output Ripple

IBUS

LOAD

–

POWER

SUPPLY

VIN

JP2 = Z

JP4 = Z

JP3 = Z

VBUS

IIN

VIN

BUS

GND

DEMO MANUAL DC2688A

Rev. 0

EVALUATE USB CHARGER PROFILES

The LT8698S/LT8698S-1 supports several common USB

charger profiles, and the DC2688A demo board is easy to

set up to evaluate these common charger profiles.

Refer to Figure9 for proper measurement equipment

setup and follow the procedure below.

1. Check that JP6 and JP7 are placed on the OFF posi-

tion, to ensure that the on-board LDOs are disabled.

2. Select JP2, JP3, and JP4 jumpers at appropriate

locations based on the desired charger profile and

SEL pin lookup table in the LT8698S/LT8698S-1 data

sheet. Table1 shows several popular USB charger

profiles available in the LT8698S/LT8698S-1. Refer

to LT8698S/LT8698S-1 data sheet for further infor-

mation about USB charger profiles.

3. With power off, connect the input power supply to

VEMI and GND turrets. If the EMI/EMC performance

is not important, connect the input power supply to

VIN and GND turrets.

4. Check that JP1 EN jumper is placed on the ONposition.

QUICK START PROCEDURE

5. Turn on the power at the input.

NOTE:Make sure that the input voltage never

exceeds42V.

6. Check for proper output voltages:V

BUS

= 5V, and D11

LED indicator lights up in green.

7. Attach a portable device to the type A socket of the

DC2688A demo board.

8. Observe the battery charging activity on the

portabledevice.

9. Observe charging current by measuring the voltage

on IMON turret:the IMON voltage should be equal to

0.46V/A in proportion to the IBUS load current.

Table1. Common USB Charger Profiles and Corresponding

SELPins

SEL1 SEL2 SEL3 CHARGER PROFILE DESCRIPTION

State 21 LOW TRI HIGH USB BC 1.2 DCP Profile

State 22 TRI TRI HIGH 2.0A Vendor Charger Profile

State 24 LOW HIGH HIGH 2.4A Vendor Charger Profile

DEMO MANUAL DC2688A

Rev. 0

Figure9. Proper Measurement Equipment Setup for Evaluating Common USB Charger Profiles

QUICK START PROCEDURE

DEMO MANUAL DC2688A

Rev. 0

EVALUATE USB BC 1.2 CDP APPLICATIONS

The LT8698S/LT8698S-1 integrates necessary hardware

to support USB BC 1.2 Charging Downstream Port (CDP)

charger profile which allows compliant devices to draw

high current of up to 1.5A from V

BUS

while simultane-

ously communicating with the host at USB high speed

of 480Mbps.

Refer to Figure10 for proper measurement equipment

setup and follow the procedure below.

1. Check that JP6 is placed on the ON position to ensure

that the 3.3V LDO is enabled.

2. Select JP2 and JP3 to be in the LOW position and

select JP4 to be in the LOW or TRI position. Select

JP4 SEL3 in the LOW position sets the LT8698S/

LT8698S-1 in select state 0 which performs the

CDP sequence with the data line switches closed

and without termination. Select JP4 SEL3 in the TRI

position sets the LT8698S/LT8698S-1 in select state

1 which performs the CDP sequence with the data line

switches open and 20k termination resistors tied from

HD+ and HD–to GND. Both select0 and select 1 are

valid state in which to start the CDP sequence. For

further information about the CDP sequence, please

refer to the LT8698S/LT8698S-1 datasheet.

3. With power off, connect the input power supply to

VEMI and GND turrets. If the EMI/EMC performance

is not important, connect the input power supply to

VIN and GND turrets.

4. Check that JP1 EN jumper is placed on the ONposition.

5. Turn on the power at the input.

NOTE:Make sure that the input voltage never

exceeds42V.

6. Check for proper output voltages:V

BUS

= 5V, and D11

LED indicator lights up in green.

7. Plug a USB cable connecting to a PC with type B

connector to the typeB socket of the DC2688A demo

board and connect the USB cable to a computer.

8. Check the STATUS pin voltage and observe STATUS

yellow LED is on, meaning STATUS pin is low. At this

point, the LT8698S/LT8698S-1 puts a 100μA current

source on the D+, asserts STATUS low and waits for

a portable device to attach to the USB socket.

9. Attach a CDP compliant portable device to the type A

socket of the DC2688A demo board.

10. Observe the CDP negotiation between the porta-

ble device and the computer. You may monitor the

voltage waveforms on STATUS, VBUS, IMON point,

D+, and D–during this CDP negotiation. Observe the

USB data connection between portable device and

the PC as manifested by the portable device showing

up in the PC in “devices and driver”or “this PC”,

and the PC may be able to access data stored in the

portabledevice.

11. To restart another CDP session, perform the

followingsteps:

a. Unplug the portable device from the type A socket.

b. Place the JP1 EN jumper to OFF position and then

place it back to ON position. Cycling the EN/UV pin

of the LT8698S/LT8698S-1 resets the CDP state

machine which is necessary in order to restart

another CPD sequence. Alternatively, the CDP state

machine can be reset by setting LT868S to a non-

CDP state (any select state other than state 0, state

1, and state 2) and coming back to state 0 or state

1. Note:in an actual CDP application, a USB host

microcontroller can detect a portable device detach

and reset the DP machine by controlling the SEL

pin(s).

c. Repeat from step 8.

QUICK START PROCEDURE

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