MYiR MYC-YT507H Manuale utente

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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MYC-YT507H

Product Manual

File State：

[ ] Draft

[ √ ] Release

FILE ID：

MYIR-MYC-YT507H-HW-PM-EN

Version：

V1.0

Author：

Dana

Created：

2022-04-13

Updated：

2022-04-13

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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History

Version

Author

Participants

Date

Description

V1.0

Dana

20220413

Initial Version

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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Contents

History.......................................................................................................................................- 2 -

Contents...................................................................................................................................- 3 -

1. Overview ............................................................................................................................................................ - 5 -

2. Product Presentation.....................................................................................................................................- 8 -

2.1. Chip Resources..............................................................................................................- 8 -

2.2. Core Board Features................................................................................................. - 11 -

2.3. Block Diagram............................................................................................................. - 12 -

2.4. Core Board Ordering Information....................................................................... - 13 -

3. Pin Description .............................................................................................................................................. - 15 -

3.1. Pin Out........................................................................................................................... - 15 -

3.2. Pin List............................................................................................................................ - 17 -

4. Electrical Characteristics .............................................................................................................................- 23 -

4.1. System Power.............................................................................................................. - 23 -

4.2. Power Consumption................................................................................................. - 24 -

4.3. GPIO DC Parameters .................................................................................................- 24 -

5. System Start-up Configuration ............................................................................................................... - 25 -

5.1. Boot Mode....................................................................................................................- 25 -

5.2. Special Function Pin..................................................................................................- 25 -

6. Interfaces .........................................................................................................................................................- 26 -

6.1. SMHC..............................................................................................................................- 26 -

6.1.1. Pin Description.................................................................................................- 26 -

6.2. UART............................................................................................................................... - 27 -

6.2.1. Pin Description.................................................................................................- 27 -

6.3. USB.................................................................................................................................. - 28 -

6.3.1. Pin Description.................................................................................................- 28 -

6.4. Ethernet......................................................................................................................... - 29 -

6.4.1. Pin Description.................................................................................................- 29 -

6.5. MIPI CSI..........................................................................................................................- 30 -

6.5.1. Pin Description.................................................................................................- 30 -

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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6.6. Parallel CSI.................................................................................................................... - 31 -

6.6.1. Pin Description.................................................................................................- 31 -

6.7. LVDS................................................................................................................................- 32 -

6.7.1. Pin Description.................................................................................................- 32 -

6.8. HDMI...............................................................................................................................- 33 -

6.8.1. Pin Description.................................................................................................- 33 -

6.9. TV CVBS Output ..........................................................................................................- 33 -

6.9.1. Pin Description.................................................................................................- 33 -

6.10. SPDIF-OUT..................................................................................................................- 34 -

6.10.1. Pin Description...............................................................................................- 34 -

6.11. I2S..................................................................................................................................- 34 -

6.11.1. Pin Description...............................................................................................- 34 -

6.12. Line Out.......................................................................................................................- 34 -

6.12.1. Pin Description...............................................................................................- 34 -

6.13. GPIO ..............................................................................................................................- 35 -

6.13.1. Pin Description...............................................................................................- 35 -

6.14. ADC...............................................................................................................................- 36 -

6.14.1. Pin Description...............................................................................................- 36 -

7. Package Information ...................................................................................................................................- 37 -

7.1. Package Dimensions.................................................................................................- 37 -

7.2. Carrier Board PCB Requirements......................................................................... - 38 -

7.3. carrier board PCB requirement.............................................................................- 39 -

Appendix A ..........................................................................................................................................................- 40 -

Warranty & Technical Support Services.................................................................... - 40 -

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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1. Overview

Allwinner T5 series is a high-performance quad-core CortexTM-A53 processor, suitable for the

new generation of automotive market. T5 series meet the test requirements of automobile AEC -

Q100. The chip integrates quad-core CortexTM-A53 CPU, G31 MP2 GPU, 32-bit DDR3 /

LPDDR3 / DDR4 / LRDDR4 dynamic random access memory. Multi-channel video output

interface (RGB / 2*LVDS / HDMI / CVBS OUT), multi-channel video input interface (MIPI CSI/

BT656/BT1120). The chip supports 4K@60fps H.265 decoding, 4K@60fps VP9 decoding,

4K@60fps AVS2 decoding, 4K@25fps H.264 encoding, 3D noise reduction as well as automatic

color matching system and trapezoidal correction module to provide a smooth user experience and

professional visual effects.

MYC-YT507H core board is based on T507-H processor, has a good software development

environment, kernel support open source operating system Linux. MYC-YT507H also has rich

interface resources. You may download the above materials at any time at the following address:

http://d.myirtech.com//MYD-YT507H/

MYC-YT507H core board is based on T507-H processor, has a good software development

environment, kernel support open source operating system Linux. MYC-YT507H also has rich

interface resources. You may download the above materials at any time at the following address:

http://www.myir-tech.com/product

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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Figure 1-1 MYC-YT507H Core board

Figure 1-2 MYD-YT507H Kit Top side

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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Figure 1-3 MYD-YT507H Kit Bottom side

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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2. Product Presentation

MYC-YT507H core board adopts SMD encapsulation form patch (stamp hole + back pad). There

are 4 standard models. They have some differences in storage configuration, temperature and

other aspects, customers can choose the appropriate model according to their needs. For the

differences between product models, see 2.4.

2.1. Chip Resources

Figure 2-1 T507-H Resource diagram

Resource

Parameter Description

CPU

Quad-core ARM CortexTM[email protected]

GPU

G31 MP2

Supports OpenGL ES 3.2/2.0/1.0,Vulkan 1.1, OpenCL 2.0

External s

torage

32-bit DDR4/DDR3/DDR3L/LPDDR3/LPDDR4 interface, supporting

maximum capacity of 4GB

SD3.0/eMMC5.0 interface

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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8-bit Nand flash interface with maximum 80-bit/1KB ECC

Video

engine

Video decoder

H.265 MP decoder up to 4K@60fps

H.264 BL/MP/HP decoder up to 4K@30fps

VP9 decoder up to 4K@60fps

AVS2 decoder up to 4K@60fps

Multi-format 1080p@60fps video playback, including VP8,

MPEG1/2 SP/MP,MPEG4 SP/ASP,

AVS+/AVS JIZHUN, VC1 SP/MP

Video encoder

H.264 encoder up to 4K@25fps

MJPEG encoder up to 4K@15fps

JPEG encoder up to 8K x 8K resolution

Video

input

Supports one 8-/10-/12-/16-bit digital camera(DC) interface

Maximum pixel clock of 148.5MHz for each DC interface

BT656,BT1120 video input for multichannel YUV

Four-lane MIPI CSI, up to l Gbps per lane in HS transmission,comp

liant with MIPI-CSI2 V1.00 and MIPI DPHY V1.00

Maximum video capture resolution of 8M@30fps or 4x 1080p@25fps

for MIPI CSI

Supports formats:YUV422,YUV420,RAW-8,RAW-10,RAW-12

Audio

Two DAC channels

Supports 1 audio output interface

(differential LINEOUTP/N or single-end LINEOUTL/LINEOUTR)

One Audio HUB, supporting internal mixing function

Embedded 3 I2S/PCM for connecting the external devices

(I2S0 for extended audio codec, I2S2 for BT, I2S3 for digital power

amplifier)

Supports Left-justified, Right-justified, Standard I2S mode,

PCM mode, and TDM mode

I2S mode supports 8 channels, and 32-bit/192kbit sample rate

I2S and TDM-modes support maximum 16 channels, and 32-bit/96kb

it sample rate

One OWA OUT interface, supporting 16-/20-/24-bit outputs

Integrated digital microphone, supporting maximum 8 digital PDM m

icrophones

Display

output

HDMI 2.0a up to 4K@60fps

TV CVBS output, supporting PAL/NTSC

LVDS interface with dual link, up to 1080p@60fps

RGB interface with DE/SYNC mode, up to 1080p@60fps

Security e

ngine

Supports Full Disk Encryption

AES, DES, 3DES, and XTS encryption and decryption algorithms

MD5, SHA, and HMAC tamper proofing

MYIR-MYC-YT507H-HW-PM-EN_V1.0

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RSA, ECC signature and verification algorithms

Supports 160-bit hardware pseudo random number generator(PRNG)

with 175-bit seed

Supports 256-bit hardware true random number generator(TRNG)

Integrated 2K-bit EFUSE for chip ID and security application

connectio

3 x USB2.0 Host, l x USB2.0 OTG

2 x Ethernet MAC (one 10/100 Mbps Ethernet port with RMII interf

ace, one 10/100/1000 Mbps

Ethernet port with RGMII and RMII interfaces)

SDIO 3.0, TSC, SCR, CIR Receiver

6 x TWI, 2 x SPI, 6 x UART

6-ch PWM, 4-ch GPADC. 1-ch LRADC

PMIC

Allwinner Power Management IC

encapsula

tion

TFBGA 421balls

15 mm x 15 mm size,0.65 mm ball pitch,0.35 mm ball size

Process

technology

28nm HPC

Table 2-1 T507-H resource

Refer to the chip manual for details.

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